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Release 6.2i - Par G.28 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Sun Nov 11 22:38:47 2007 NOTE: This file is designed to be imported into a spreadsheet program such as Microsoft E

-- E:\资料\计算机设计与实践\MYCPU16 -- VHDL Test Bench created by -- HDL Bencher 6.1i -- Sun Nov 11 22:40:14 2007 -- -- Notes: -- 1) This testbench has been automatically generated from -- your Test B

-- E:\资料\计算机设计与实践\CPU_16\CPU_16 -- VHDL Test Bench created by -- HDL Bencher 6.1i -- Sat Nov 10 14:17:45 2007 -- -- Notes: -- 1) This testbench has been automatically generated from -- your

Release 6.2i - Par G.28 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Sun Nov 11 22:38:47 2007 INPUT FILE: clock_map.ncd OUTPUT FILE: clock_pad.txt PART TYPE: xcv200

xst -intstyle ise -ifn __projnav/clock.xst -ofn clock.syr ngdbuild -intstyle ise -dd e:\资料\计算机设计与实践\mycpu16/_ngo -i -p xcv200-pq240-4 clock.ngc clock.ngd map -intstyle ise -p xcv200-pq240-4 -cm are

Creating the nc1 file as track file

-- E:\资料\计算机设计与实践\MYCPU16 -- VHDL Annotation Test Bench created by -- HDL Bencher 6.1i -- Sun Nov 11 22:40:14 2007 LIBRARY IEEE; USE IEEE.STD_LOGIC_ARITH.ALL; LIBRARY UNISIM; USE UNISIM.VCOMPONE

### uVision2 Project, (C) Keil Software ### Do not modify ! Target (Target 1), 0x0000 // Tools: 'MCS-51' Group (Source Group 1) File 1,1, 0x0 File 1,1,

### uVision2 Project, (C) Keil Software ### Do not modify ! cExt (*.c) aExt (*.s*; *.src; *.a*) oExt (*.obj) lExt (*.lib) tExt (*.txt; *.h; *.inc) pExt (*.plm) CppX (*.cpp) DaveTm {