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Clock 的代码
complete_clock.v
module complete_clock(LED_Hr,LED_Min,LED_Sec,CP,ALARM,_1kHz,AdjMinkey,AdjHrkey,
SetHrkey,SetMinkey,CtrlBell,Mode,nCR);
input _1kHz,CP;
input nCR;
output [7:0]LED_Hr,LED_Min,LED_Sec;
wir
top_clock.ttf
255,255, 98,255, 37, 0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,
96, 24,134, 97, 24,150, 9
complete_clock.hif
HIF003
--
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, an
complete_clock.ttf
255,255, 98,255, 37, 0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,
96, 24,134, 97, 24,150, 9
top_clock.v
module top_clock (Hour,Minute,Second,CP,EN,nCR,Adj_Min,Adj_Hour);
input CP,EN,nCR,Adj_Min,Adj_Hour;
output[7:0] Hour,Minute,Second;
wire[7:0] Hour,Minute,Second;
supply1 Vdd;
wire Min_CP,Ho
top_clock.fit
-- MAX+plus II Compiler Fit File
-- Version 10.2 07/10/2002
-- Compiled: 12/15/2008 16:42:26
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and