complete_clock.v

数字钟 可实现正常计数校准 还有方电台报时功能 四低一高 闹钟功能

module complete_clock(LED_Hr,LED_Min,LED_Sec,CP,ALARM,_1kHz,AdjMinkey,AdjHrkey,
						SetHrkey,SetMinkey,CtrlBell,Mode,nCR);
	input _1kHz,CP;
	input nCR;
	output [7:0]LED_Hr,LED_Min,LED_Sec;
	wire[7:0]LED_Hr,LED_Min,LED_Sec;
	wire _500Hz;
	input AdjMinkey,AdjHrkey;
	wire[7:0]Hour,Minute,Second;
	input SetHrkey,SetMinkey;
	wire[7:0]Set_Hr,Set_Min;
	wire Alarm_Clock;
	wire Alarm_Radio;
	output ALARM;
	input CtrlBell;
	input Mode;
	Divided_Frequency C0(_1KHz,_500Hz);
	top_clock C1(Hour,Minute,Second,CP,nCR,AdjMinkey,AdjHrkey);
	Radio C2(ALARM_Radio,Minute,Second,_1kHz,_500Hz);
	Bell C3(ALARM_Clock,Set_Hr,Set_Min,Hour,Minute,Second,
		SetHrKey,SetMinKey,_1kHz,_500Hz,CP,CtrlBell);
	assign ALARM=ALARM_Radio||ALARM_Clock;
	_2to1MUX MU1(LED_Hr,Mode,Set_Hr,Hour);
	_2to1MUX MU2(LED_Min,Mode,Set_Min,Minute);
	_2to1MUX MU3(LED_Sec,Mode,8'h00,Second);
	endmodule