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Clock 的代码
clock.ncd
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.4
###5460:XlxV32DM 3fff 153ceNrNWm2P2ziS/ivBIh9mdrDdYlHvRIC4bbdtRLIdy0m698MIkl/2+u4myU1uB3NoJ7/9qihKJinK6V7kgANik/VUsVhVrCpR7byEJHhkTLzcHP54+PLw6WP6gl
clock.pcf
//! **************************************************************************
// Written by: Map H.38 on Tue Jul 01 23:12:06 2008
//! ***************************************************************
clock.ucf
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "HALARM" LOC = "P65" ;
NET "ALMCLR" LOC = "P81" ;
NET "ALMSETH" LOC = "P78" ;
NET "ALMSETM"
clock.xst
set -tmpdir __projnav
set -xsthdpdir ./xst
run
-ifn CLOCK.prj
-ifmt mixed
-ofn CLOCK
-ofmt NGC
-p xcv100-4-pq240
-top CLOCK
-opt_mode Speed
-opt_level 1
-iuc NO
-lso CLOCK.lso
-keep_hiera
clock.bld
Release 7.1i ngdbuild H.38
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Command Line: ngdbuild -intstyle ise -dd "c:\documents and
settings\administrator\桌面\数字钟/_ngo" -uc CLOCK.ucf -p
clock.par
Release 7.1i par H.38
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
0D89A88209E84A6:: Tue Jul 01 23:12:07 2008
par -w -intstyle ise -ol std -t 1 CLOCK_map.ncd CLOCK.ncd CLOCK.pcf
Co
clock.drc
WARNING:PhysDesignRules:372 - Gated clock. Clock net XLXN_56 is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-fl