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test_clock.v

module testbench_clock; wire clk; clock c (clk); test t (clk); endmodule module test(clk); input clk; initial begin $monitor($time,,,"clock=%b",clk); #50 $stop;

clock-rc.rc

#ifndef WORKSHOP_INVOKED #include #endif S1 WAV gotup.wav S2 WAV wolf.wav I1 ICON 1.ico I2 ICON 11.ico

clock-arch.h

/* * Copyright (c) 2006, Swedish Institute of Computer Science. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provide

clock-arch.c

/* * Copyright (c) 2006, Swedish Institute of Computer Science. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provide

clock1.ttf

255,255, 98,255, 37, 0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255, 96, 24,134, 97, 24,134, 9

clock1.pin

-- Copyright (C) 1988-2002 Altera Corporation -- Any megafunction design, and related net list (encrypted or decrypted), -- support information, device programming or simulation file, and any other

clock1.hex

:020000040000FA :2B000000FFFF62FF2500FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF76 :2B002B00601886611886611886611886611886611886010000000018866118866118866118866118866