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Clock 的代码
sec_clock.pin
-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and a
sec_clock.vho
-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any o
sec_clock.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
sec_clock.hif
Version 7.2 Build 151 09/26/2007 SJ Full Version
38
2246
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Path
sec_clock.pss
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5ce5222920398e6723e7127f59cf5f6
sec_clock.vhd
library ieee;
use ieee.std_logic_1164.all;
entity sec_clock is
port( clk:in std_logic;
rst:in std_logic;
start:in std_logic;
sel:out std_logic_vector(7 downto 0);
d
sec_clock.done
Wed Oct 08 20:20:17 2008