sec_clock.vho

基于CYCLONE系列FPGA EP1C3T144C8的VHDL秒表代码

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 7.2 Build 151 09/26/2007 SJ Full Version"

-- DATE "10/08/2008 20:20:16"

-- 
-- Device: Altera EP1C3T144C8 Package TQFP144
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, cyclone;
USE IEEE.std_logic_1164.all;
USE cyclone.cyclone_components.all;

ENTITY 	sec_clock IS
    PORT (
	clk : IN std_logic;
	rst : IN std_logic;
	start : IN std_logic;
	sel : OUT std_logic_vector(7 DOWNTO 0);
	data : OUT std_logic_vector(7 DOWNTO 0)
	);
END sec_clock;

ARCHITECTURE structure OF sec_clock IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_rst : std_logic;
SIGNAL ww_start : std_logic;
SIGNAL ww_sel : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_data : std_logic_vector(7 DOWNTO 0);
SIGNAL \num[16]~243\ : std_logic;
SIGNAL \num[16]~243COUT1\ : std_logic;
SIGNAL \num[17]~245\ : std_logic;
SIGNAL \num[17]~245COUT1\ : std_logic;
SIGNAL \num[0]~247\ : std_logic;
SIGNAL \num[0]~247COUT1\ : std_logic;
SIGNAL \num[1]~249\ : std_logic;
SIGNAL \num[1]~249COUT1\ : std_logic;
SIGNAL \num[2]~251\ : std_logic;
SIGNAL \num[2]~251COUT1\ : std_logic;
SIGNAL \num[3]~253\ : std_logic;
SIGNAL \num[4]~255\ : std_logic;
SIGNAL \num[4]~255COUT1\ : std_logic;
SIGNAL \num[5]~257\ : std_logic;
SIGNAL \num[5]~257COUT1\ : std_logic;
SIGNAL \num[6]~259\ : std_logic;
SIGNAL \num[6]~259COUT1\ : std_logic;
SIGNAL \num[7]~261\ : std_logic;
SIGNAL \num[7]~261COUT1\ : std_logic;
SIGNAL \num[8]~263\ : std_logic;
SIGNAL \num[9]~265\ : std_logic;
SIGNAL \num[9]~265COUT1\ : std_logic;
SIGNAL \num[10]~267\ : std_logic;
SIGNAL \num[10]~267COUT1\ : std_logic;
SIGNAL \num[11]~269\ : std_logic;
SIGNAL \num[11]~269COUT1\ : std_logic;
SIGNAL \num[12]~271\ : std_logic;
SIGNAL \num[12]~271COUT1\ : std_logic;
SIGNAL \num[13]~273\ : std_logic;
SIGNAL \num[14]~275\ : std_logic;
SIGNAL \num[14]~275COUT1\ : std_logic;
SIGNAL \num[15]~277\ : std_logic;
SIGNAL \num[15]~277COUT1\ : std_logic;
SIGNAL \clk1~regout\ : std_logic;
SIGNAL \LessThan0~279_combout\ : std_logic;
SIGNAL \LessThan0~280_combout\ : std_logic;
SIGNAL \LessThan0~281_combout\ : std_logic;
SIGNAL \LessThan0~282_combout\ : std_logic;
SIGNAL \LessThan0~283_combout\ : std_logic;
SIGNAL \LessThan0~284_combout\ : std_logic;
SIGNAL \LessThan0~285_combout\ : std_logic;
SIGNAL \clk~combout\ : std_logic;
SIGNAL \start~combout\ : std_logic;
SIGNAL \rst~combout\ : std_logic;
SIGNAL \Add2~162_combout\ : std_logic;
SIGNAL \P2:scan[0]~regout\ : std_logic;
SIGNAL \Add2~163\ : std_logic;
SIGNAL \Add2~163COUT1\ : std_logic;
SIGNAL \Add2~164_combout\ : std_logic;
SIGNAL \P2:scan[1]~regout\ : std_logic;
SIGNAL \Add2~165\ : std_logic;
SIGNAL \Add2~165COUT1\ : std_logic;
SIGNAL \Add2~166_combout\ : std_logic;
SIGNAL \P2:scan[2]~regout\ : std_logic;
SIGNAL \Add2~167\ : std_logic;
SIGNAL \Add2~167COUT1\ : std_logic;
SIGNAL \Add2~168_combout\ : std_logic;
SIGNAL \P2:scan[3]~regout\ : std_logic;
SIGNAL \Add2~169\ : std_logic;
SIGNAL \Add2~169COUT1\ : std_logic;
SIGNAL \Add2~174_combout\ : std_logic;
SIGNAL \P2:scan[4]~regout\ : std_logic;
SIGNAL \Add2~175\ : std_logic;
SIGNAL \Add2~176_combout\ : std_logic;
SIGNAL \P2:scan[5]~regout\ : std_logic;
SIGNAL \Add2~177\ : std_logic;
SIGNAL \Add2~177COUT1\ : std_logic;
SIGNAL \Add2~170_combout\ : std_logic;
SIGNAL \P2:scan[6]~regout\ : std_logic;
SIGNAL \Add2~171\ : std_logic;
SIGNAL \Add2~171COUT1\ : std_logic;
SIGNAL \Add2~172_combout\ : std_logic;
SIGNAL \P2:scan[7]~regout\ : std_logic;
SIGNAL \Add2~173\ : std_logic;
SIGNAL \Add2~173COUT1\ : std_logic;
SIGNAL \Add2~178_combout\ : std_logic;
SIGNAL \P2:scan[8]~regout\ : std_logic;
SIGNAL \Add2~179\ : std_logic;
SIGNAL \Add2~179COUT1\ : std_logic;
SIGNAL \Add2~180_combout\ : std_logic;
SIGNAL \P2:scan[9]~regout\ : std_logic;
SIGNAL \Add2~181\ : std_logic;
SIGNAL \Add2~182_combout\ : std_logic;
SIGNAL \P2:scan[10]~regout\ : std_logic;
SIGNAL \Equal0~100_combout\ : std_logic;
SIGNAL \Equal0~98\ : std_logic;
SIGNAL \Equal0~99\ : std_logic;
SIGNAL \Equal0~101_combout\ : std_logic;
SIGNAL \Equal18~84_combout\ : std_logic;
SIGNAL \Equal18~85_combout\ : std_logic;
SIGNAL \Equal18~86_combout\ : std_logic;
SIGNAL \Equal18~87_combout\ : std_logic;
SIGNAL \Equal18~88_combout\ : std_logic;
SIGNAL \sel~111_combout\ : std_logic;
SIGNAL \Equal18~89_combout\ : std_logic;
SIGNAL \Equal18~90_combout\ : std_logic;
SIGNAL \rst1~regout\ : std_logic;
SIGNAL \start1~regout\ : std_logic;
SIGNAL \Equal1~42_combout\ : std_logic;
SIGNAL \led_5[0]~288_combout\ : std_logic;
SIGNAL \Equal2~42_combout\ : std_logic;
SIGNAL \led_6[0]~258_combout\ : std_logic;
SIGNAL \Equal3~42_combout\ : std_logic;
SIGNAL \led_5[0]~290_combout\ : std_logic;
SIGNAL \led_5[3]~291_combout\ : std_logic;
SIGNAL \Equal4~42_combout\ : std_logic;
SIGNAL \led_4~630_combout\ : std_logic;
SIGNAL \Equal5~46_combout\ : std_logic;
SIGNAL \led_2~361_combout\ : std_logic;
SIGNAL \led_4[1]~634_combout\ : std_logic;
SIGNAL \led_4~631_combout\ : std_logic;
SIGNAL \led_3[1]~421_combout\ : std_logic;
SIGNAL \led_3~418_combout\ : std_logic;
SIGNAL \Equal6~39_combout\ : std_logic;
SIGNAL \led_1[1]~139_combout\ : std_logic;
SIGNAL \led_2~364_combout\ : std_logic;
SIGNAL \Equal7~39_combout\ : std_logic;
SIGNAL \led_2~362_combout\ : std_logic;
SIGNAL \led_1[1]~140_combout\ : std_logic;
SIGNAL \seg[2]~213_combout\ : std_logic;
SIGNAL \seg[2]~214_combout\ : std_logic;
SIGNAL \seg[2]~211_combout\ : std_logic;
SIGNAL \seg[2]~212_combout\ : std_logic;
SIGNAL \seg[2]~215_combout\ : std_logic;
SIGNAL \seg[0]~228_combout\ : std_logic;
SIGNAL \seg[0]~229_combout\ : std_logic;
SIGNAL \seg[0]~226_combout\ : std_logic;
SIGNAL \seg[0]~227_combout\ : std_logic;
SIGNAL \seg[0]~230_combout\ : std_logic;
SIGNAL \seg[1]~223_combout\ : std_logic;
SIGNAL \seg[1]~224_combout\ : std_logic;
SIGNAL \seg[1]~221_combout\ : std_logic;
SIGNAL \seg[1]~222_combout\ : std_logic;
SIGNAL \seg[1]~225_combout\ : std_logic;
SIGNAL \seg[3]~216_combout\ : std_logic;
SIGNAL \seg[3]~217_combout\ : std_logic;
SIGNAL \seg[3]~218_combout\ : std_logic;
SIGNAL \seg[3]~219_combout\ : std_logic;
SIGNAL \seg[3]~220_combout\ : std_logic;
SIGNAL \data~1042_combout\ : std_logic;
SIGNAL \Equal17~235_combout\ : std_logic;
SIGNAL \Equal17~234_combout\ : std_logic;
SIGNAL \Equal17~236_combout\ : std_logic;
SIGNAL \data~1040_combout\ : std_logic;
SIGNAL \data~1041_combout\ : std_logic;
SIGNAL \data~1043_combout\ : std_logic;
SIGNAL \Equal17~241_combout\ : std_logic;
SIGNAL \Equal17~237_combout\ : std_logic;
SIGNAL \Equal17~240_combout\ : std_logic;
SIGNAL \Equal17~238_combout\ : std_logic;
SIGNAL \Equal17~239_combout\ : std_logic;
SIGNAL \data~1044_combout\ : std_logic;
SIGNAL \data~1045_combout\ : std_logic;
SIGNAL \data~1046_combout\ : std_logic;
SIGNAL \data~1047_combout\ : std_logic;
SIGNAL \data~1048_combout\ : std_logic;
SIGNAL \data~1049_combout\ : std_logic;
SIGNAL \data~1050_combout\ : std_logic;
SIGNAL \data~1051_combout\ : std_logic;
SIGNAL \data~1055_combout\ : std_logic;
SIGNAL \data~1052_combout\ : std_logic;
SIGNAL \data~1053_combout\ : std_logic;
SIGNAL \data~1054_combout\ : std_logic;
SIGNAL led_1 : std_logic_vector(3 DOWNTO 0);
SIGNAL led_2 : std_logic_vector(3 DOWNTO 0);
SIGNAL led_3 : std_logic_vector(3 DOWNTO 0);
SIGNAL led_4 : std_logic_vector(3 DOWNTO 0);
SIGNAL led_7 : std_logic_vector(3 DOWNTO 0);
SIGNAL led_8 : std_logic_vector(3 DOWNTO 0);
SIGNAL num : std_logic_vector(18 DOWNTO 0);
SIGNAL seclect : std_logic_vector(2 DOWNTO 0);
SIGNAL led_5 : std_logic_vector(3 DOWNTO 0);
SIGNAL led_6 : std_logic_vector(3 DOWNTO 0);
SIGNAL \ALT_INV_rst1~regout\ : std_logic;
SIGNAL \ALT_INV_start~combout\ : std_logic;

BEGIN

ww_clk <= clk;
ww_rst <= rst;
ww_start <= start;
sel <= ww_sel;
data <= ww_data;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
\ALT_INV_rst1~regout\ <= NOT \rst1~regout\;
\ALT_INV_start~combout\ <= NOT \start~combout\;

\num[16]\ : cyclone_lcell
-- Equation(s):
-- num(16) = DFFEAS(num(16) $ (!(!\num[13]~273\ & \num[15]~277\) # (\num[13]~273\ & \num[15]~277COUT1\)), GLOBAL(\clk~combout\), VCC, , , , , \LessThan0~285_combout\, )
-- \num[16]~243\ = CARRY(num(16) & (!\num[15]~277\))
-- \num[16]~243COUT1\ = CARRY(num(16) & (!\num[15]~277COUT1\))

-- pragma translate_off
GENERIC MAP (
	cin0_used => "true",
	cin1_used => "true",
	cin_used => "true",
	lut_mask => "a50a",
	operation_mode => "arithmetic",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	synch_mode => "on")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	dataa => num(16),
	aclr => GND,
	sclr => \LessThan0~285_combout\,
	cin => \num[13]~273\,
	cin0 => \num[15]~277\,
	cin1 => \num[15]~277COUT1\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => num(16),
	cout0 => \num[16]~243\,
	cout1 => \num[16]~243COUT1\);

\num[17]\ : cyclone_lcell
-- Equation(s):
-- num(17) = DFFEAS(num(17) $ (!\num[13]~273\ & \num[16]~243\) # (\num[13]~273\ & \num[16]~243COUT1\), GLOBAL(\clk~combout\), VCC, , , , , \LessThan0~285_combout\, )
-- \num[17]~245\ = CARRY(!\num[16]~243\ # !num(17))
-- \num[17]~245COUT1\ = CARRY(!\num[16]~243COUT1\ # !num(17))

-- pragma translate_off
GENERIC MAP (
	cin0_used => "true",
	cin1_used => "true",
	cin_used => "true",
	lut_mask => "3c3f",
	operation_mode => "arithmetic",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	synch_mode => "on")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	datab => num(17),
	aclr => GND,
	sclr => \LessThan0~285_combout\,
	cin => \num[13]~273\,
	cin0 => \num[16]~243\,
	cin1 => \num[16]~243COUT1\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => num(17),
	cout0 => \num[17]~245\,
	cout1 => \num[17]~245COUT1\);

\num[0]\ : cyclone_lcell
-- Equation(s):
-- num(0) = DFFEAS(!num(0), GLOBAL(\clk~combout\), VCC, , , , , \LessThan0~285_combout\, )
-- \num[0]~247\ = CARRY(num(0))
-- \num[0]~247COUT1\ = CARRY(num(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "55aa",
	operation_mode => "arithmetic",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "on")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	dataa => num(0),
	aclr => GND,
	sclr => \LessThan0~285_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => num(0),
	cout0 => \num[0]~247\,
	cout1 => \num[0]~247COUT1\);

\num[1]\ : cyclone_lcell
-- Equation(s):
-- num(1) = DFFEAS(num(1) $ (\num[0]~247\), GLOBAL(\clk~combout\), VCC, , , , , \LessThan0~285_combout\, )
-- \num[1]~249\ = CARRY(!\num[0]~247\ # !num(1))
-- \num[1]~249COUT1\ = CARRY(!\num[0]~247COUT1\ # !num(1))

-- pragma translate_off
GENERIC MAP (
	cin0_used => "true",
	cin1_used => "true",
	lut_mask => "5a5f",
	operation_mode => "arithmetic",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	synch_mode => "on")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	dataa => num(1),
	aclr => GND,
	sclr => \LessThan0~285_combout\,
	cin0 => \num[0]~247\,
	cin1 => \num[0]~247COUT1\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => num(1),
	cout0 => \num[1]~249\,
	cout1 => \num[1]~249COUT1\);

\num[2]\ : cyclone_lcell
-- Equation(s):
-- num(2) = DFFEAS(num(2) $ !\num[1]~249\, GLOBAL(\clk~combout\), VCC, , , , , \LessThan0~285_combout\, )
-- \num[2]~251\ = CARRY(num(2) & !\num[1]~249\)
-- \num[2]~251COUT1\ = CARRY(num(2) & !\num[1]~249COUT1\)

-- pragma translate_off
GENERIC MAP (
	cin0_used => "true",
	cin1_used => "true",
	lut_mask => "c30c",
	operation_mode => "arithmetic",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	synch_mode => "on")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	datab => num(2),
	aclr => GND,
	sclr => \LessThan0~285_combout\,
	cin0 => \num[1]~249\,
	cin1 => \num[1]~249COUT1\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => num(2),
	cout0 => \num[2]~251\,
	cout1 => \num[2]~251COUT1\);

\num[3]\ : cyclone_lcell
-- Equation(s):
-- num(3) = DFFEAS(num(3) $ \num[2]~251\, GLOBAL(\clk~combout\), VCC, , , , , \LessThan0~285_combout\, )
-- \num[3]~253\ = CARRY(!\num[2]~251COUT1\ # !num(3))

-- pragma translate_off
GENERIC MAP (
	cin0_used => "true",
	cin1_used => "true",
	lut_mask => "3c3f",
	operation_mode => "arithmetic",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	synch_mode => "on")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	datab => num(3),
	aclr => GND,
	sclr => \LessThan0~285_combout\,
	cin0 => \num[2]~251\,
	cin1 => \num[2]~251COUT1\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => num(3),
	cout => \num[3]~253\);

\num[4]\ : cyclone_lcell
-- Equation(s):
-- num(4) = DFFEAS(num(4) $ !\num[3]~253\, GLOBAL(\clk~combout\), VCC, , , , , \LessThan0~285_combout\, )
-- \num[4]~255\ = CARRY(num(4) & !\num[3]~253\)
-- \num[4]~255COUT1\ = CARRY(num(4) & !\num[3]~253\)

-- pragma translate_off
GENERIC MAP (
	cin_used => "true",
	lut_mask => "c30c",
	operation_mode => "arithmetic",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	synch_mode => "on")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	datab => num(4),
	aclr => GND,
	sclr => \LessThan0~285_combout\,
	cin => \num[3]~253\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => num(4),
	cout0 => \num[4]~255\,
	cout1 => \num[4]~255COUT1\);

\num[5]\ : cyclone_lcell
-- Equation(s):
-- num(5) = DFFEAS(num(5) $ ((!\num[3]~253\ & \num[4]~255\) # (\num[3]~253\ & \num[4]~255COUT1\)), GLOBAL(\clk~combout\), VCC, , , , , \LessThan0~285_combout\, )
-- \num[5]~257\ = CARRY(!\num[4]~255\ # !num(5))
-- \num[5]~257COUT1\ = CARRY(!\num[4]~255COUT1\ # !num(5))

-- pragma translate_off
GENERIC MAP (
	cin0_used => "true",
	cin1_used => "true",
	cin_used => "true",
	lut_mask => "5a5f",
	operation_mode => "arithmetic",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	synch_mode => "on")