代码搜索：Clock

找到约 10,000 项符合「Clock」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/411439/11245818

opt clock.opt

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www.eeworm.com/read/411428/11245908

vhd clock.vhd

---------------------------------------------------------------------------------------------------------------------- --This top module combined 3 modules:second,minute,hour.It is used as a clock.
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www.eeworm.com/read/411307/11248897

res clock.res

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www.eeworm.com/read/411307/11248902

dpr clock.dpr

{****************************************************************************** * Program Clock * Description: * To show a transparent window as a clock on desktop. * Support time
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www.eeworm.com/read/265935/11249031

bmp clock.bmp

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www.eeworm.com/read/265670/11258022

cpp clock.cpp

#include #include #include using namespace std; struct MemPCB { int pageId; //process_id bool accessed; //whether is accessed bool modifi
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www.eeworm.com/read/265643/11259199

gyd clock.gyd

Pin Freeze File: version E.33 9510884 XC95108-7-PC84 keyen S:PIN55 clk S:PIN9 keyclr S:PIN54 lddat S:PIN40 lddat S:PIN41 lddat S:PIN43 lddat S:PIN44 lddat S:PIN45 lddat
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www.eeworm.com/read/265643/11259200

jid clock.jid

. clock clock.v f:\实验\xilinx\clock\clock.v
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www.eeworm.com/read/265643/11259202

xst clock.xst

set -tmpdir . set -overwrite YES run -ifmt VERILOG -top clock -p XC9500 -ifn clock.prj -opt_mode Speed -opt_level 1 -check_attribute_syntax YES -keep_hierarchy YES -fsm_extract YES -fsm_enc
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www.eeworm.com/read/265643/11259204

_prj clock._prj

insert `timescale 1ns/1ns include include clock.v include d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
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