代码搜索结果
找到约 10,000 项符合
Clock 的代码
clock.v
module clock(clk,clk_1k,mode,change,turn,alert,hour,min,sec,
LD_alert,LD_hour,LD_min);
input clk,clk_1k,mode,change,turn;
output alert,LD_alert,LD_hour,LD_min;
output[7:0] hour,min,sec;
reg[7:0]
clock.pin
-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions,
clock.cdf
/* Quartus II Version 5.0 Build 148 04/26/2005 SJ Full Version */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(EPM1270T144) Path("") File("clock.pof
clock.hif
Version 5.0 Build 148 04/26/2005 SJ Full Version
33
1689
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
clock
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# so
clock.pin
-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions,
clock.cdf
/* Quartus II Version 5.0 Build 148 04/26/2005 SJ Full Version */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(EPM1270T144) Path("") File("clock.pof
clock.hif
Version 5.0 Build 148 04/26/2005 SJ Full Version
33
1689
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
clock
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# so