clock.hif

来自「一个用verilog编写的数字时钟」· HIF 代码 · 共 38 行

Version 5.0 Build 148 04/26/2005 SJ Full Version
33
1689
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
clock
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
clock.v
1134542706
7
# storage
db|clock.(0).cnf
db|clock.(0).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
|
}
# end
# complete