代码搜索：Carry
找到约 8,060 项符合「Carry」的源代码
代码结果 8,060
www.eeworm.com/read/416598/11019877
s rand.s
AREA |subr|, CODE, READONLY
EXPORT randomnumber
randomnumber
; on exit:
; a1 = low 32-bits of pseudo-random number
; a2 = high bit (if you want to know it)
LDR ip, |seedpointer|
www.eeworm.com/read/270376/11040862
c cpue.c
#include "sysdeps.h"
#include "shared.h"
#include "memory.h"
#include "custom.h"
#include "newcpu.h"
#include "cputbl.h"
void op_e000(ULONG opcode)
{
ULONG srcreg = imm8_table[(opcode & 3584) >> 9];
www.eeworm.com/read/470055/6923900
cpp dsa.cpp
// dsa.cpp - written and placed in the public domain by Wei Dai
#include "pch.h"
#ifndef CRYPTOPP_IMPORTS
#include "dsa.h"
#include "nbtheory.h"
NAMESPACE_BEGIN(CryptoPP)
size_t DSACon
www.eeworm.com/read/379840/6958595
s rand.s
AREA |subr|, CODE, READONLY
EXPORT randomnumber
randomnumber
; on exit:
; a1 = low 32-bits of pseudo-random number
; a2 = high bit (if you want to know it)
LDR ip, |seedpointer|
www.eeworm.com/read/466104/7038205
vhd cnt60.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cnt60 is
port( ch,cl : buffer std_logic_vector (3 downto 0);
clk : in st
www.eeworm.com/read/329914/7109657
bak cnt60.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cnt60 is
port( ch,cl : buffer std_logic_vector (3 downto 0);
clk : in st
www.eeworm.com/read/329914/7109658
vhd cnt60.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cnt60 is
port( ch,cl : buffer std_logic_vector (3 downto 0);
clk : in st
www.eeworm.com/read/461365/7228579
vhd cnt60.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cnt60 is
port( ch,cl : buffer std_logic_vector (3 downto 0);
clk : in st
www.eeworm.com/read/460207/7255727
bak countu3d5_tb.v.bak
module countu3d5_tb;
reg rst,clk,up,dn;
reg [7:0]din;
wire[7:0]dout;
wire par,carry,borrow;
initial din=8'b11010011;
always #1 clk=~clk;
initial begin
clk=0;
www.eeworm.com/read/460207/7255732
v counta3d5_tb.v
module counta3d5_tb;
reg rst,clk,up,dn;
reg [7:0]din;
wire[7:0]dout;
wire par,carry,borrow;
initial din=8'b11010011;
always #1 clk=~clk;
initial begin
clk=0;