代码搜索：Carry
找到约 8,060 项符合「Carry」的源代码
代码结果 8,060
www.eeworm.com/read/17885/764167
vhd fen60.vhd
-------------------------------------------------
--功 能：60进制计数器
--接 口：clk -时钟输入
-- qout1-个位BCD输出
-- qout2-十位BCD输出
-- carry-进位信号输出
------------------------------------
www.eeworm.com/read/479931/1327488
ms mulv32.ms
# mach: crisv32
# output: fffffffe\n
# output: ffffffff\n
# output: fffffffe\n
# output: 1\n
# output: fffffffe\n
# output: ffffffff\n
# output: fffffffe\n
# output: 1\n
; Check that carry is not mod
www.eeworm.com/read/464789/1525087
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity BarrelShift is
port(
out_ShiftOut : out vl_logic_vector(31 downto 0);
out_Carry : out vl_logic;
in_ShiftIn
www.eeworm.com/read/453029/1646611
vhd fen60.vhd
-------------------------------------------------
--功 能：60进制计数器
--接 口：clk -时钟输入
-- qout1-个位BCD输出
-- qout2-十位BCD输出
-- carry-进位信号输出
------------------------------------
www.eeworm.com/read/346457/3182807
svn-base check_mulv32.s.svn-base
# mach: crisv32
# output: fffffffe\n
# output: ffffffff\n
# output: fffffffe\n
# output: 1\n
# output: fffffffe\n
# output: ffffffff\n
# output: fffffffe\n
# output: 1\n
; Check that carry is not mod
www.eeworm.com/read/346457/3182851
s check_mulv32.s
# mach: crisv32
# output: fffffffe\n
# output: ffffffff\n
# output: fffffffe\n
# output: 1\n
# output: fffffffe\n
# output: ffffffff\n
# output: fffffffe\n
# output: 1\n
; Check that carry is not mod
www.eeworm.com/read/287791/4018106
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity BarrelShift is
port(
out_ShiftOut : out vl_logic_vector(31 downto 0);
out_Carry : out vl_logic;
in_ShiftIn
www.eeworm.com/read/385462/2590193
s check_mulv32.s
# mach: crisv32
# output: fffffffe\n
# output: ffffffff\n
# output: fffffffe\n
# output: 1\n
# output: fffffffe\n
# output: ffffffff\n
# output: fffffffe\n
# output: 1\n
; Check that carry is not mod
www.eeworm.com/read/379467/2673630
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity BarrelShift is
port(
out_ShiftOut : out vl_logic_vector(31 downto 0);
out_Carry : out vl_logic;
in_ShiftIn
www.eeworm.com/read/370236/9607593
txt mul32c.vhdl.txt
-- mul32c.vhdl parallel multiply 32 bit x 32 bit to get 64 bit unsigned product
-- uses add32 component and fadd component, includes carry save
-- uses VHDL 'generate' to hav