_primary.vhd

来自「arm7的IP软核代码」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity BarrelShift is
    port(
        out_ShiftOut    : out    vl_logic_vector(31 downto 0);
        out_Carry       : out    vl_logic;
        in_ShiftIn      : in     vl_logic_vector(31 downto 0);
        in_ShiftCount   : in     vl_logic_vector(4 downto 0);
        in_ShiftType    : in     vl_logic_vector(1 downto 0);
        in_ShiftCountInReg: in     vl_logic;
        in_ShiftCountHigh3Bit: in     vl_logic_vector(2 downto 0);
        in_Operand2IsReg: in     vl_logic;
        in_Carry        : in     vl_logic
    );
end BarrelShift;