代码搜索：Carry
找到约 8,060 项符合「Carry」的源代码
代码结果 8,060
www.eeworm.com/read/165570/5481464
java depositcommand.java
package Commands;
import Interfaces.*;
import Sets.*;
import SystemEntities.*;
import Accounts.*;
import dslib.exception.ItemNotFoundUosException;
/** Command to carry out a deposit. The co
www.eeworm.com/read/298155/3876062
dat asslandat50.dat
带进位加法指令 ADC(Addition Carry)
格式: ADC OPRD1,OPRD2
----
功能: OPRD1
www.eeworm.com/read/269755/11079134
cpp newmat2.cpp
/// \ingroup newmat
///@{
/// \file newmat2.cpp
/// Matrix row and column operations.
/// The operations on individual rows and columns used to carry out matrix
/// add, multiply etc.
// C
www.eeworm.com/read/139904/13120945
v musicpro.v
/* 乐曲演奏电路子模块 */
module musicpro(clk_6M,clk_4,speaker,high,mid,low,carry);
input clk_6M,clk_4; //clk_6M: 用于产生各种音阶频率的基准频率；clk_4: 用于控制音长（节拍）的时钟频率
output speaker,carry; //speaker：用于激励扬声器的输出信号，为
www.eeworm.com/read/449504/7503118
m adf.m
function results = adf(x,p,l)
% PURPOSE: carry out DF tests on a time-series vector
%---------------------------------------------------
% USAGE: results = adf(x,p,nlag)
% where: x = a time-seri
www.eeworm.com/read/241378/13148351
v rbcla_adder.v
//
// S.Arvind
// 2/3/99
// Ripple-Block Carry Look Ahead Adder
// Reference: Computer Arithmetic Algorithms - Israel Koren
// Computer Arithmetic Systems - Amos R. Om
www.eeworm.com/read/309611/13667769
h bn_mul.h
/**
* \file bn_mul.h
*/
/*
* Multiply source vector [s] with b, add result
* to destination vector [d] and set carry c.
*
* Currently supports:
*
* . IA-32 (386+)
www.eeworm.com/read/309608/13667841
h bn_mul.h
/**
* \file bn_mul.h
*/
/*
* Multiply source vector [s] with b, add result
* to destination vector [d] and set carry c.
*
* Currently supports:
*
* . IA-32 (386+)
www.eeworm.com/read/116193/14983399
cpp carrycrt.cpp
#include "ap.h"
// Carry & Chinese Remainder Theorem for fnt-multiplication (and square)
// Returns 1 if right shift ocurred
// Assume that ds1 will be in memory if possible
int carrycrt (ap
www.eeworm.com/read/14022/292111
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity carry_sum is
port(
sin : in vl_logic;
cin : in vl_logic;
sout : out vl_logic