代码搜索：Carry
找到约 8,060 项符合「Carry」的源代码
代码结果 8,060
www.eeworm.com/read/125697/14470284
txt adder_nbit_generate.txt
-- n-bit Adder using the Generate Statement
-- download from: www.fpga.com.cn & www.pld.com.cn
library IEEE;
use IEEE.Std_logic_1164.all;
ENTITY addn IS
GENERIC(n : POSITIVE := 3); --no.
www.eeworm.com/read/370579/9595087
txt 加法器：generate语句的应用.txt
-- n-bit Adder using the Generate Statement
-- download from: www.fpga.com.cn & www.pld.com.cn
library IEEE;
use IEEE.Std_logic_1164.all;
ENTITY addn IS
GENERIC(n : POSITIVE := 3); --no.
www.eeworm.com/read/173672/9643794
vhd count60.vhd
Library IEEE;
Use IEEE.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity count60 is
Port(carry: in std_logic;--from 1Hz input clock or the full_index of
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vhd count24.vhd
Library IEEE;
Use IEEE.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity count24 is
Port(carry: in std_logic;--from 1Hz input clock or the full_index of
www.eeworm.com/read/369385/9651542
vhd addn.vhd
-- n-bit Adder using the Generate Statement
-- download from: www.fpga.com.cn & www.pld.com.cn
library IEEE;
use IEEE.Std_logic_1164.all;
ENTITY addn IS
GENERIC(n : POSITIVE := 3); -
www.eeworm.com/read/335443/12522734
vhd times.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TIMES IS
PORT(CLR:IN STD_LOGIC;
CLK:IN STD_LOGIC;
ENA:IN STD_LOGIC;
DOUT:OUT STD_LOGIC_VECTOR(23 DOWNTO 0));
END TIM
www.eeworm.com/read/139799/13130648
vhd example11-21.vhd
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY full_adder IS
GENERIC (delay_sum, delay_carry : TIME);
PORT (in1, in2, carry_in : IN Std_Logic;
sum, carry_out : OUT Std_Logic);
END
www.eeworm.com/read/176099/9516673
vhdl fulladder.vhdl
-- $Id: fulladder.vhdl,v 1.1.1.1 2005/01/04 02:05:58 arif_endro Exp $
-------------------------------------------------------------------------------
-- Title : Full Adder component
-- Project
www.eeworm.com/read/176092/9516843
eqn cnt60.map.eqn
-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any o
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eqn fir31.fit.eqn
--A1L6 is fout4[0]~0COUT0 at LC_X41_Y21_N3
--operation mode is arithmetic
A1L6_cout_0 = A1L102 & A1L252;
A1L6 = CARRY(A1L6_cout_0);
--A1L7 is fout4[0]~0COUT1 at LC_X41_Y21_N3
--operation mode