times.vhd

vhdl语言编写秒表程序 内含每个模块的源程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TIMES IS
   PORT(CLR:IN STD_LOGIC;
        CLK:IN STD_LOGIC;
        ENA:IN STD_LOGIC;
        DOUT:OUT STD_LOGIC_VECTOR(23 DOWNTO 0));
END TIMES;
ARCHITECTURE ART OF TIMES IS
   COMPONENT CLKGEN
     PORT(CLK:IN STD_LOGIC;
          NEWCLK:OUT STD_LOGIC);
END COMPONENT;
COMPONENT CNT10
   PORT(CLK,CLR,ENA:IN STD_LOGIC;
        CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        CARRY_OUT:OUT STD_LOGIC);
END COMPONENT;
COMPONENT CNT6
   PORT(CLK,CLR,ENA:IN STD_LOGIC;
        CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        CARRY_OUT:OUT STD_LOGIC);
END COMPONENT;
SIGNAL NEWCLK:STD_LOGIC;
  SIGNAL CARRY1:STD_LOGIC;
  SIGNAL CARRY2:STD_LOGIC;
  SIGNAL CARRY3:STD_LOGIC;
  SIGNAL CARRY4:STD_LOGIC;
  SIGNAL CARRY5:STD_LOGIC;
  BEGIN
  U0:CLKGEN PORT MAP(CLK=>CLK,NEWCLK=>NEWCLK);
  U1:CNT10 PORT MAP(CLK=>NEWCLK,CLR=>CLR,ENA=>ENA,
          CQ=>DOUT(3 DOWNTO 0),CARRY_OUT=>CARRY1);
  U2:CNT10 PORT MAP(CLK=>CARRY1,CLR=>CLR,ENA=>ENA,
          CQ=>DOUT(7 DOWNTO 4),CARRY_OUT=>CARRY2);
  U3:CNT10 PORT MAP(CLK=>CARRY2,CLR=>CLR,ENA=>ENA,
          CQ=>DOUT(11 DOWNTO 8),CARRY_OUT=>CARRY3);
  U4:CNT6 PORT MAP(CLK=>CARRY3,CLR=>CLR,ENA=>ENA,
         CQ=>DOUT(15 DOWNTO 12),CARRY_OUT=>CARRY4);
  U5:CNT10 PORT MAP(CLK=>CARRY4,CLR=>CLR,ENA=>ENA,
          CQ=>DOUT(19 DOWNTO 16),CARRY_OUT=>CARRY5);
  U6:CNT6 PORT MAP(CLK=>CARRY5,CLR=>CLR,ENA=>ENA,
         CQ=>DOUT(23 DOWNTO 20));
END ART;