代码搜索：CS2
找到约 499 项符合「CS2」的源代码
代码结果 499
www.eeworm.com/read/269205/4246877
v case_decode.v
// Use case statement to build decode circuit without prior
`timescale 1ns/1ps
module case_decode (addr_H, CS1, CS2, CS3, CS4);
input [2:0] addr_H;
output CS1, CS2, CS3, CS4;
reg [3
www.eeworm.com/read/436051/1855279
asm lcd.asm
//==========================================说明=============================================
// DI/RS:IOB3 R/W:IOB4 E:IOB5 CS1:IOB6 CS2:IOB7
// CS1和CS2只能有一个为低
//程序规范：每个函数写数据前自己清零数
www.eeworm.com/read/429003/1952318
v if_single_decode.v
// Use case statement to build decode circuit without prior
`timescale 1ns/1ps
module if_single_decode (addr_H, CS1, CS2, CS3, CS4);
input [2:0] addr_H;
output CS1, CS2, CS3, CS4;
reg
www.eeworm.com/read/429003/1952355
v if_mult_decode.v
// Use case statement to build decode circuit without prior
`timescale 1ns/1ps
module if_mult_decode (addr_H, CS1, CS2, CS3, CS4);
input [2:0] addr_H;
output CS1, CS2, CS3, CS4;
reg [
www.eeworm.com/read/429003/1952399
v case_decode.v
// Use case statement to build decode circuit without prior
`timescale 1ns/1ps
module case_decode (addr_H, CS1, CS2, CS3, CS4);
input [2:0] addr_H;
output CS1, CS2, CS3, CS4;
reg [3
www.eeworm.com/read/421122/10754359
v led2.v
module LED2(a,b,c,d,e,f,g,CS1,CS2,D3,D2,D1,D0,CLK);
output a,b,c,d,e,f,g,CS1,CS2;
input D3,D2,D1,D0,CLK;
reg a,b,c,d,e,f,g,CS1,CS2;
reg r3,r2,r1,r0;
reg[7:0] buffer;
always @(posedge CL
www.eeworm.com/read/418779/10902333
txt 11267.txt
Rule
--
Sid
11267
--
Summary:
This event is generated when an attempt is made to exploit a known vulnerability in .
--
Impact:
High
--
Detailed Information:
Buffer overflow in Adobe Photoshop CS2
www.eeworm.com/read/464869/7061547
v uart_top.v
module uart_top(clk,rst,send,send_data,send_over,error,recv,
recv_data,rxd1,txd1,rxd2,txd2,cs1,cs2);
input clk,rst,send,rxd1,rxd2,cs1,cs2;
input[7:0] send_data;
www.eeworm.com/read/464869/7061549
v send_register.v
module send_register(clk,rst,ce,din,txd1,txd2,cs1,cs2);
input clk,rst,ce,cs1,cs2;
input[9:0] din;
output txd1,txd2;
reg txd1,txd2;
reg[9:0] s_buf;
always @(posedge clk or neg
www.eeworm.com/read/166091/10036399
c lcd12231.c
//XDM9602@SINA.COM
/*------------------------------------------------------------------------------------------------------------------------------------
接口端：1：VDD、2：GND、3：VLCD、4：RET、5：CS1、6：CS2、7