代码搜索：CPLD FPGA
找到约 10,000 项符合「CPLD FPGA」的源代码
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www.eeworm.com/read/236583/14010124
h cpld.h
#ifndef _cpld_
#define cpld
#else
#define cpld extern
#endif
#define SETRCK P4DIR|=BIT0;P4OUT|=BIT0;
#define CLRRCK P4DIR|=BIT0;P4OUT&=~BIT0;
www.eeworm.com/read/236033/14035066
h cpld.h
#include "reg52.h"
#include "absacc.h"
#define Busy 0x80 // 忙判别位
#pragma SAVE
#pragma REGPARMS
extern unsigned char adc(unsigned char a);
extern void da(unsigned char addr,unsigned c
www.eeworm.com/read/235401/14072545
pdf cpld.pdf
www.eeworm.com/read/204973/15330757
c cpld.c
/*7218在硬件译码的时候，低四位数据进行译码，最高位控制小数点，其余三位无效*/
// distab保存要显示的8位数据（每一位为一个字节）
// ledtab为7218软件译码字型表
#include
#include
#define DisCmd XBYTE [0xC100] //7218控制字地址
www.eeworm.com/read/204973/15330782
src cpld.src
; .\CPLD.SRC generated from: CPLD.C
; COMPILER INVOKED BY:
; C:\Keil\C51\BIN\C51.EXE CPLD.C BROWSE DEBUG OBJECTEXTEND SRC(.\CPLD.SRC)
$NOMOD51
NAME CPLD
P0 DATA 080H
P1 DATA 090H
P
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obj cpld.obj
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lst cpld.lst
C51 COMPILER V7.06 CPLD 07/22/2005 20:23:23 PAGE 1
C51 COMPILER V7.06, COMPILATION OF MODULE CPLD
OBJECT MODULE PLACED IN CP
www.eeworm.com/read/202499/15380377
vhd cpld.vhd
--fpga FPP(fast passive parallel) configuration
--fpga_conf_done in ：The FPGA will release the pin high when configuration is successful.配置成功后置高
--fpga_nstatus in ：FPGA pulls the pin low if a con
www.eeworm.com/read/202189/15389985
h cpld.h
/************************************************************/
/* define base addresses */
/************************************************************/
#def
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