代码搜索:CPLD FPGA

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www.eeworm.com/read/17540/737541

cpld

www.eeworm.com/read/17540/737542

cpld

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; PACKAGE ram_constants IS constant DATA_WIDTH : INTEGER := 8; constant ADDR_WIDTH : I
www.eeworm.com/read/17540/737543

cpld

--2选1电路方法1 --library ieee; --use ieee.std_logic_1164.all; --entity mux2_1 is --port(d0,d1,sel:in std_logic; --q:out std_logic); --end mux2_1; --architecture beh of mux2_1 is -
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cpld

Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reg4 IS PORT( d:in std_logic_vector(3 downto 0); ci: IN std_logic; clk : IN std_logic; q:out std_logic_vector(3 downto 0);
www.eeworm.com/read/17540/737545

cpld

library ieee; use ieee.std_logic_1164.all; entity or2a is port ( a: in bit ; b: in bit ; c: out bit); end or2a; architecture rtl of or2a is begin c
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cpld

/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to
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cpld

/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/17540/737548

cpld

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity adder4bit is port(cin:in std_logic; a,b:in std_logic_vector(3 downto 0); s:out std_logic_vector(3 downto
www.eeworm.com/read/17540/737549

cpld

Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reg8 IS PORT( d_1:in std_logic_vector(3 downto 0); d_2:in std_logic_vector(3 downto 0); clk: IN std_logic; q_1:out std_logic_v
www.eeworm.com/read/17540/737550

cpld

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; package dp16 is function add(a:std_logic_vector; b:std_logic_vector) return std