代码搜索：CPLD FPGA
找到约 10,000 项符合「CPLD FPGA」的源代码
代码结果 10,000
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cpld
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY AD574_2 IS
PORT ( D : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
CLK ,STATUS : IN STD_LOGIC;
OUT4 : OUT STD_LOGIC_VECTOR
www.eeworm.com/read/17540/737642
cpld
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY AD574_1 IS
PORT (D :IN STD_LOGIC_VECTOR(11 DOWNTO 0);
CLK ,STATUS : IN STD_LOGIC;--状态机时钟CLK，AD574状态信号STATUS
LOCK0 : OUT
www.eeworm.com/read/17540/737643
cpld
-- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: dff_8.vhd
-- Megafun
www.eeworm.com/read/17540/737644
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk is
port(
clk : in std_logic;
address : out std_logic_vector(5 downto 0));
end clk;
a
www.eeworm.com/read/17540/737645
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mux8_2 is
generic(n:integer:=24);
port(
sel:in bit;
A,B:in std_logic_vector(7 downto 0);
Y:out std_logi
www.eeworm.com/read/17540/737646
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mux2_1 is
generic(n:integer:=24);
port(
sel:in bit;
A,B:in std_logic;
Y:out std_logic);
end mux2_1;
a
www.eeworm.com/read/17540/737647
cpld
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/17540/737648
cpld
fbc_rom_inst : fbc_rom PORT MAP(
address => address_sig,
inclock => inclock_sig,
outclock => outclock_sig,
q => q_sig
);
www.eeworm.com/read/17540/737649
cpld
#include
#include //文件操作，访问I/O全靠它了
#include //控制台I/O, getch()之类的
#include
//多媒体的，我的程序中用到了多媒体定时器，一般windows定
//时器，精度差。而多媒体定时器精度高，可精确到1mS.所以跟硬件打交道的时候就很
//有用了。
/
www.eeworm.com/read/17540/737650
cpld
package slotwidth is
constant sreg_width :integer:=20;
end slotwidth;
use work.defcon.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.a