cpld

《CPLD开发实例》的配套光盘文件

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY AD574_2 IS
    PORT (        D : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
        CLK ,STATUS : IN STD_LOGIC;
               OUT4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                  Q : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) );
END AD574_2;
ARCHITECTURE behav OF AD574_2 IS
SIGNAL  current_state, next_state: STD_LOGIC_VECTOR(4 DOWNTO 0 );
  CONSTANT st0 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "11100" ;
  CONSTANT st1 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00001" ;
  CONSTANT st2 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000" ;
  CONSTANT st3 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00100" ;
  CONSTANT st4 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00110" ;
  SIGNAL REGL   : STD_LOGIC_VECTOR(11 DOWNTO 0);
  SIGNAL LK     : STD_LOGIC; 
 BEGIN                               
 COM1: PROCESS(current_state,STATUS)   --决定转换状态的进程
BEGIN 
 CASE current_state IS           
  WHEN st0 => next_state <= st1;
  WHEN st1 => next_state <= st2;                    
  WHEN st2 => IF (STATUS='1') THEN next_state <= st2; 
                 ELSE    next_state <= st3;                
                 END IF ;
  WHEN st3=>  next_state <= st4;  
  WHEN st4=>  next_state <= st0;  
  WHEN OTHERS => next_state <= st0;     
     END CASE ;
   OUT4 <= current_state(4 DOWNTO 1);
 END PROCESS COM1 ;
  REG: PROCESS (CLK)  -- 时序进程  
     BEGIN
       IF ( CLK'EVENT AND CLK='1')  THEN   
      current_state <= next_state; 
      END IF;
   END PROCESS REG; 
      LK <=  current_state(1) ;
  LATCH1 : PROCESS ( LK ) -- 数据锁存器进程
      BEGIN
       IF LK='1' AND LK'EVENT THEN   
         REGL <= D ;       
END IF;
  END PROCESS ; 
          Q <= REGL;  
END behav;