代码搜索：CPLD FPGA
找到约 10,000 项符合「CPLD FPGA」的源代码
代码结果 10,000
www.eeworm.com/read/17540/737631
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mux3to1 is
port(a ,c:in std_logic;
b :in std_logic;
sela,selb:in std_logi
www.eeworm.com/read/17540/737632
cpld
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/17540/737633
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mux2to1 is
port(a :in std_logic;
b :in std_logic;
sel:in std_logic;
c
www.eeworm.com/read/17540/737634
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mux3to1_1 is
port(a,c :in std_logic;
b :in std_logic;
sel1,sel2:in std_lo
www.eeworm.com/read/17540/737635
cpld
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY seq_check IS
PORT(DIN,clk,clr:IN STD_LOGIC; --串行输入数据位/工作时钟/复位信号
AB:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); --检测结果输出
END seq_check;
www.eeworm.com/read/17540/737636
cpld
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY s_machine IS
PORT ( clk,reset : IN STD_LOGIC;
state_inputs : IN STD_LOGIC_VECTOR (0 TO 1);
comb_outputs : OUT INTEGER RA
www.eeworm.com/read/17540/737637
cpld
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY AD0809 IS
PORT ( D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --0809的8位转换数据输出
CLK ,EOC : IN STD_LOGIC; --CLK是转换工作时钟
L
www.eeworm.com/read/17540/737638
cpld
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MEALY1 IS
PORT ( CLK ,DATAIN,RESET : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
END MEALY1;
ARCHITECTURE behav OF MEALY1
www.eeworm.com/read/17540/737639
cpld
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
ENTITY state_m2 IS
PORT(clk, reset, nw : in std_logic;
sel: out std_logic_vector(1 down
www.eeworm.com/read/17540/737640
cpld
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MOORE1 IS
PORT (DATAIN :IN STD_LOGIC_VECTOR(1 DOWNTO 0);
CLK,RST : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(3 DOWNTO