代码搜索：CPLD FPGA
找到约 10,000 项符合「CPLD FPGA」的源代码
代码结果 10,000
www.eeworm.com/read/17540/737621
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder_4_16 is
port(a1,b1,c1,d1,g2a1,g2b1:in std_logic;
y1,y2:out std_logi
www.eeworm.com/read/17540/737622
cpld
---------------二输入与门程序模块--------------
library ieee;
use ieee.std_logic_1164.all;
entity myand1 is
port(a,b:in std_logic;
q :out std_logic);
end myand1;
architecture rtl of myand1 is
begin
q
www.eeworm.com/read/17540/737623
cpld
library ieee;
use ieee.std_logic_1164.all;
entity x_or2 is
port (
in1 : in bit ;
in2 : in bit ;
out1 : out bit) ;
end x_or2;
entity and_gate is
port (
a : in bit ;
b : in bit ;
c :
www.eeworm.com/read/17540/737624
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity myand is
GENERIC (sreg_width:integer:=8); --n输入与门,n=sreg_width
por
www.eeworm.com/read/17540/737625
cpld
library ieee;
use ieee.std_logic_1164.all;
entity x_or is
port (
in1 : in bit ;
in2 : in bit ;
out1 : out bit);
end x_or;
architecture rtl of x_or is
begin
out1
www.eeworm.com/read/17540/737626
cpld
---------------二输入或门程序模块（行为级）--------------
library ieee;
use ieee.std_logic_1164.all;
entity x_or1 is
port (
in1 : in bit ;
in2 : in bit ;
out1 : out bit) ;
end x_or1;
architecture behavior
www.eeworm.com/read/17540/737627
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fifo1 is
port(
clk: in std_logic; --定义控制时钟
reset: in std_logic;
www.eeworm.com/read/17540/737628
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo is
port( DataIn :in std_logic_vector(7 downto 0);
DataOut :out std_logic_vector(7 downto 0);
clk
www.eeworm.com/read/17540/737629
cpld
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fifo2 IS
PORT(data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); --输入数据
wrreq : IN STD_LOGIC ; --写入请求
rd
www.eeworm.com/read/17540/737630
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mux4to1 is
port(a,b,c,d:in std_logic;
sel:in std_logic_vector(1 downto 0);