cpld

《CPLD开发实例》的配套光盘文件

library ieee;
use ieee.std_logic_1164.all;

entity x_or2 is
port (
	in1 : in bit ;
	in2 : in bit ;
	out1 : out bit) ;
end x_or2;
entity and_gate is
port (
	a : in bit ;
	b : in bit ;
	c : out bit) ;
end and_gate;

architecture behavior of and_gate is
begin
process(a,b)
begin
	c <= a and b after 5 ns;
end process;
end behavior;
entity or_gate is
port (
	d : in bit ;
	e : in bit ;
	f : out bit) ;
end or_gate;

architecture behavior of or_gate is
begin
process(d,e)
begin
	f <= d or e after 4 ns;
end process;
end behavior;

entity inverter is
port (
	g : in bit ;
	h : out bit) ;
end inverter;
architecture behavior of inverter is
begin
process(g)
begin
	h <= not g after 3 ns;
end process;
end behavior;

architecture structural of x_or2 is
						-- signal定义
	signal t1, t2, t3, t4 : bit;
						-- component定义
	component and_gate
		port (a, b : in bit; c : out bit) ;
	end component;
	component or_gate
		port (d, e : in bit; f : out bit) ;
	end component;
	component inverter
		port (g : in bit; h : out bit) ;
	end component;
	begin
					-- 元件例化
	u0: and_gate port map ( a => t1, b => in2, c => t3);
	u1: and_gate port map ( a => in1, b => t2, c => t4);
	u2: inverter port map ( g => in1, h => t1);
	u3: inverter port map ( g => in2, h => t2);
	u4: or_gate port map ( d => t3, e => t4, f => out1);
end structural;