代码搜索：CAN Bus
找到约 10,000 项符合「CAN Bus」的源代码
代码结果 10,000
www.eeworm.com/read/18159/778055
v can_testbench.v
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
`include "can_testbench_defines.v"
module can_testbench();
parameter Tp = 1;
paramet
www.eeworm.com/read/18159/778057
stx can_registers.stx
Release 6.1i - xst G.23
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to .
CPU : 0.00 / 0.82 s | Elapsed : 0.00 / 0.00 s
--> WARNING:Xst:1885 - LSO file is empt
www.eeworm.com/read/18159/778060
bld can_top.bld
Release 6.1i - ngdbuild G.23
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
Command Line: ngdbuild -intstyle ise -dd
e:\program\fpga_program\for_fpga\can\ise\canbus/_ngo -i -p xc2s300e-p
www.eeworm.com/read/18159/778062
v can_register.v
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
module can_register
( data_in,
data_out,
we,
clk
);
parameter WIDTH = 8; // default parameter of the re
www.eeworm.com/read/18159/778064
v can_crc.v
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
module can_crc (clk, data, enable, initialize, crc);
parameter Tp = 1;
input clk;
input data;
www.eeworm.com/read/18159/778065
fdo can_testbench.fdo
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jan 11 10:15:14 中国标准时间 2005
##
vlib work
vlog can_register_asyn_syn.v
vlog can_register_asyn.v
vlog can_regi
www.eeworm.com/read/18159/778066
v can_defines.v
// Uncomment following line if you want to use WISHBONE interface. Otherwise
// 8051 interface is used.
// `define CAN_WISHBONE_IF
// Uncomment following line if you want to use CAN in Ac
www.eeworm.com/read/18159/778069
prj can_top.prj
verilog work can_register_asyn_syn.v
verilog work can_register_asyn.v
verilog work can_register.v
verilog work can_registers.v
verilog work can_btl.v
verilog work can_crc.v
verilog work can_acf.
www.eeworm.com/read/18159/778077