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CAN Bus 的代码
switch_bus.jhd
MODULE switch_bus
switch_bus.vhd
-- 库声明
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- 实体声明
entity switch_bus is
-- 类属参数
generic (
BUS_WIDTH : integer := 8 ); -- 总线宽度
port (
din1 : in std_logic_vector(BUS_WIDTH-1 d
cpld_bus.bdf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
bus_ism.v
module bus_ISM(PSEN_N,ALE_E,addr_data,WR_N,
RD_N,addr_match,data_trs,data_oe,clk,reset);
input PSEN_N,ALE_E;
input reset;
input clk;
inout [7:0] addr_data;
input WR_N;
input RD_N;
input a
cpld_bus.pin
-- Copyright (C) 1991-2004 Altera Corporation
-- Any megafunction design, and related netlist (encrypted or decrypted),
-- support information, device programming or simulation file, and a
cpld_bus.qpf
# Copyright (C) 1991-2004 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any oth
cpld_bus.vwf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
cpld_bus.qws
[ProjectWorkspace]
ptn_Child1=Frames
ptn_Child2=Workmode
ptn_Child3=ActionPoints
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
pt