代码搜索：Behavioural
找到约 91 项符合「Behavioural」的源代码
代码结果 91
www.eeworm.com/read/360708/10080970
vhd clockdiv.vhd
library ieee;
use ieee.std_logic_1164.all;
entity clockdiv is
port(
clockin : in std_logic;
clockout : out std_logic );
end clockdiv;
architecture behavioural of clockdiv is
www.eeworm.com/read/469746/6926040
vhd clockdiv.vhd
library ieee;
use ieee.std_logic_1164.all;
entity clockdiv is
port(
clockin : in std_logic;
clockout : out std_logic );
end clockdiv;
architecture behavioural of clockdiv is
www.eeworm.com/read/443322/7634617
vhd gequ.vhd
library ieee;
use ieee.std_logic_1164.all;
entity gequ is
port(
clockin : in std_logic;
clockout : out std_logic );
end gequ;
architecture behavioural of gequ is
signal clock_i
www.eeworm.com/read/161948/10355470
vhd hehe.vhd
library ieee;
use ieee.std_logic_1164.all;
entity d_ff is
port(D,res,clock : in std_logic;
Q : out std_logic);
end entity d_ff;
architecture behavioural of d_ff is
begin
p0: process(clock)
b
www.eeworm.com/read/469753/6926214
vhd clockdiv4.vhd
library ieee;
use ieee.std_logic_1164.all;
entity clockdiv4 is
port(
clockin : in std_logic;
clockout : out std_logic );
end clockdiv4;
architecture behavioural of clockdiv4 is
www.eeworm.com/read/469753/6926225
vhd clockdiv6.vhd
library ieee;
use ieee.std_logic_1164.all;
entity clockdiv6 is
port(
clockin : in std_logic;
clockout : out std_logic );
end clockdiv6;
architecture behavioural of clockdiv6 is
www.eeworm.com/read/443322/7634619
vhd clockdiv4.vhd
library ieee;
use ieee.std_logic_1164.all;
entity clockdiv4 is
port(
clockin : in std_logic;
clockout : out std_logic );
end clockdiv4;
architecture behavioural of clockdiv4 is
www.eeworm.com/read/443322/7634630
bak gequ.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
entity clockdiv6 is
port(
clockin : in std_logic;
clockout : out std_logic );
end clockdiv6;
architecture behavioural of clockdiv6 is
www.eeworm.com/read/346092/11769383
vhd reg32bit.vhd
library ieee;
use ieee.std_logic_1164.all;
entity reg is
generic (n : natural := 32);
port (D : in std_logic_vector(31 downto 0);
Clock, Reset, Enable : in std_logic;
Q : out std_logic_vector(31 downt
www.eeworm.com/read/457722/7318732
vhd cpuwaitgenerator.vhd
--************************************************************************************************
-- Behavioural description of cpuwait generator for AVR microcontroller (for simulation)
-- Version