hehe.vhd

DDS 的设计应用 DDS 的设计应用

library ieee;
use ieee.std_logic_1164.all;
entity d_ff is
port(D,res,clock : in std_logic;
      Q : out std_logic);
end entity d_ff;
architecture behavioural of d_ff is
begin
p0: process(clock)
    begin
   if (clock = '1' and clock'event) then
     if(res='0')then  
      Q<= '0'; 
     else          
      Q <= D;
     end if;
   end if;  
    end process;
end behavioural;

--一位加法器程序
library ieee;
use ieee.std_logic_1164.all;
entity adder1 is
port(a, b, cin : in std_logic;
      sum, cout :out std_logic);
end entity adder1;
architecture behavioural of adder1 is
begin
sum <= a xor b xor cin;
cout <= (a and b) or (a and cin) or (b and cin);
end architecture behavioural;

--累加程序
library ieee;
use ieee.std_logic_1164.all;
entity leijia1 is
port(A, res,clock : in std_logic;
      Q1 ,cout1 : out std_logic);
end  leijia1;
architecture behavioural of leijia1 is

component d_ff
  port(D,res, clock : in std_logic;
       Q : out std_logic);
end component;
component adder1
  port(a, b, cin : in std_logic;
       sum, cout : out std_logic);
end component;
signal a1,b1,e1 ,cin,cout_r: std_logic;
begin
u1: d_ff port map(D=>A, res=>res,clock=>clock, Q=>a1);
u2: d_ff port map(D=>e1, res=>res,clock=>clock, Q=>b1);
u3: d_ff port map(D=>cout_r, res=>res,clock=>clock, Q=>cin);
u4: adder1 port map(a=>a1, b=>b1, cin=>cin, cout=>cout_r, sum=>e1);
u5: d_ff port map(D=>e1, res=>res,clock=>clock, Q=>Q1);
u6: d_ff port map (D=>cout_r,res=>res,clock=>clock,Q=>cout1);
end behavioural;