代码搜索：Behavior
找到约 3,820 项符合「Behavior」的源代码
代码结果 3,820
www.eeworm.com/read/345569/11808561
changes
2007/04/10 - MiraXT V1.1 released:
- Output behavior "SAT Competition" compatible.
- Data type "unsigned int" instead of "int" used
to store the literal ac
www.eeworm.com/read/344239/11895134
java notclasses.java
//: enumerated/NotClasses.java
// {Exec: javap -c LikeClasses}
import static net.mindview.util.Print.*;
enum LikeClasses {
WINKEN { void behavior() { print("Behavior1"); } },
BLINKEN { void
www.eeworm.com/read/344239/11895137
java overrideconstantspecific.java
//: enumerated/OverrideConstantSpecific.java
import static net.mindview.util.Print.*;
public enum OverrideConstantSpecific {
NUT, BOLT,
WASHER {
void f() { print("Overridden method"); }
www.eeworm.com/read/154463/11956779
java showtext3d.java
package showtext3d;
import java.awt.*;
import java.awt.event.*;
import java.applet.Applet;
import java.awt.BorderLayout;
import java.awt.event.*;
import java.awt.GraphicsConfiguration;
import java.aw
www.eeworm.com/read/342479/12017474
vhd fpq.vhd
library ieee;
use ieee.std_logic_1164.all;
entity fpq is
generic ( n:integer:=10);
port ( clk:in std_logic;
en: in std_logic;
clkout:out std_logic);
end fpq;
architec
www.eeworm.com/read/153614/12021012
vhd 36_gcd.vhd
entity gcd is
port(start: in bit;
clk : in bit;
din : in bit;
xi,yi: in integer;
dout : out bit;
output:out integer);
end gcd;
architecture behavior of gcd is
begin
process
www.eeworm.com/read/151305/12220462
vhd 36_gcd.vhd
entity gcd is
port(start: in bit;
clk : in bit;
din : in bit;
xi,yi: in integer;
dout : out bit;
output:out integer);
end gcd;
architecture behavior of gcd is
begin
process
www.eeworm.com/read/339117/12256615
css mod_euro2008.css
div#euro2008-banner {
position: absolute;
top: 0px;
right: 0px;
z-index: 9999;
}
div#euro2008-banner img {
border: 0px !important;
}
* html div#euro2008-banner img {
behavior: url(
www.eeworm.com/read/252132/12300265
vhd downcnt.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY downcnt IS
GENERIC ( modulus : INTEGER := 8 ) ;
PORT ( Clock, L, E : IN STD_LOGIC ;
Q : OUT INTEGER RANGE 0 TO modulus-1 ) ;
END d
www.eeworm.com/read/252132/12300366
vhd problem.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY problem IS
PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
En : IN STD_LOGIC ;
y0, y1, y2, y3 : OUT STD_LOGIC ) ;
END proble