代码搜索：Assignment

找到约 8,196 项符合「Assignment」的源代码

代码结果 8,196
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/214382/15104073

tlg ddr_sdram.tlg

Selecting top level module ddr_sdram Synthesizing module pll1 Synthesizing module ddr_control_interface Synthesizing module ddr_command @W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\sy
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www.eeworm.com/read/214382/15104095

tlg ddr_data_path.tlg

Selecting top level module ddr_sdram Synthesizing module pll1 Synthesizing module ddr_control_interface Synthesizing module ddr_command @W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\sy
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www.eeworm.com/read/213274/15138362

qsf f_adder.qsf

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any
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www.eeworm.com/read/213274/15138472

qmsg h_adder.fit.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartu
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www.eeworm.com/read/162614/5520927

c 14664-2.c

// { dg-do assemble } // { dg-options "-fpermissive -w" } // 981203 bkoz // g++/14664 + test char foo[26]; void bar() { // the addition of the flag "-fno-const-string-literal" reverts to pre-ISO.
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www.eeworm.com/read/162614/5522085

c 900324_05.c

// { dg-do assemble } // g++ 1.37.1 bug 900324_05 // The following erroneous code causes g++ to segfault. // Cfront 2.0 passes this test. // keywords: segfault, arrays, references, assignment oper
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www.eeworm.com/read/162614/5530396

c ssa-dse-5.c

/* { dg-do compile } */ /* { dg-options "-O2 -fdump-tree-optimized" } */ int x; int f1 (int i, int j, int k) { int *p = k ? &i : &j; i = 3; *p = 5; x = j; } /* The assignment "i =
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www.eeworm.com/read/154076/5643152

tlg alu.tlg

Selecting top level module alu Synthesizing module alu @W:"J:\Project_Navigator_Demo\alu_vlog\ALU.V":28:4:28:7|Latch generated from always block for signal outp_a[7:0], probably caused by a missing
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www.eeworm.com/read/154076/5643169

tlg alu.tlg

Selecting top level module alu Synthesizing module alu @N:"J:\Project_Navigator_Demo\alu_vlog\ALU.V":23:20:23:25|Removing redundant assignment @W:"J:\Project_Navigator_Demo\alu_vlog\ALU.V":29:4:29:
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www.eeworm.com/read/475739/6776811

qsf clk_div.qsf

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu
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