alu.tlg

Xinx ISE 官方源代码盘第二章

Selecting top level module alu
Synthesizing module alu
@N:"J:\Project_Navigator_Demo\alu_vlog\ALU.V":23:20:23:25|Removing redundant assignment
@W:"J:\Project_Navigator_Demo\alu_vlog\ALU.V":29:4:29:7|Latch generated from always block for signal outp_a[7:0], probably caused by a missing assignment in an if or case stmt