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signal
`timescale 1ns/1ns
`difine timeslice 200
module Signal(RESET,CLK,RD,WR,ADDR,ACK,DATA);
output RESET;
output CLK;
output RD,WR;
output[10:0]ADDR;
input ACK;
inout[7:0] DATA;
reg RESET;
reg CLK;`timesca