代码搜索：Add
找到约 10,000 项符合「Add」的源代码
代码结果 10,000
www.eeworm.com/read/17609/742470
vhd shift_add.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity shift_add is
port(indata:in std_logic_vector(10 downto 0);
clk:in std_logic;
add_en: in std_logic;
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gdf add8.gdf
www.eeworm.com/read/17609/742672
gdf add4.gdf
www.eeworm.com/read/17609/742733
vhd add_a_f.vhd
--addr_a_f
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addr_a_f is
port(
sel: in std_logic_vector( 1 downto 0);
sel_a_f: in std_logic;
www.eeworm.com/read/17631/743852
vhd add_sub.vhd
-- megafunction wizard: %LPM_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_add_sub
-- ============================================================
-- File Name: add_sub.vhd
www.eeworm.com/read/17631/743858
bsf add_sub.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/17631/744001
vhd add_qf.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity add_qf is
port( qk:in std_logic_vector(7 downto 0);-----前馈量
fk:in std_logic_vector(7 downto 0);-----
www.eeworm.com/read/17631/746817
qpf half_add.qpf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/17631/746819
vhd half_add.vhd
library ieee;
use ieee.std_logic_1164.all;
entity half_add is
port(a,b:in std_logic;
s,c:out std_logic);
end;
architecture one of half_add is
begin
s
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