代码搜索：1Hz
找到约 197 项符合「1Hz」的源代码
代码结果 197
www.eeworm.com/read/282522/4097775
txt 2103_rtc_interrupt.txt
Specifications:
1. Create a 1Hz interrupt using RTC second interrupt
2. Configure RTC as IRQ interrupt
3. Toggel LED 4 at 0.5Hz rate
4. Ensure that PLL is disengaged by clearing PLLE and PLLC an
www.eeworm.com/read/407445/2265184
txt 2103_rtc_interrupt.txt
Specifications:
1. Create a 1Hz interrupt using RTC second interrupt
2. Configure RTC as IRQ interrupt
3. Toggel LED 4 at 0.5Hz rate
4. Ensure that PLL is disengaged by clearing PLLE and PLLC an
www.eeworm.com/read/370209/2786574
txt 2103_rtc_interrupt.txt
Specifications:
1. Create a 1Hz interrupt using RTC second interrupt
2. Configure RTC as IRQ interrupt
3. Toggel LED 4 at 0.5Hz rate
4. Ensure that PLL is disengaged by clearing PLLE and PLLC an
www.eeworm.com/read/384939/8833107
txt clock.txt
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY clock IS
PORT(clk: IN STD_LOGIC; --system clock,1hz
settim
www.eeworm.com/read/443073/7638614
vhd clock.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY clock IS
PORT(clk: IN STD_LOGIC; --system clock,1hz
settim
www.eeworm.com/read/304086/13801182
vhd clock.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY clock IS
PORT(clk: IN STD_LOGIC; --system clock,1hz
settim
www.eeworm.com/read/404551/11483064
vhd clock.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY clock IS
PORT(clk: IN STD_LOGIC; --system clock,1hz
settim
www.eeworm.com/read/5905/81015
tdf guibrain.tdf
FUNCTION debounce (left_button, right_button, clk)
RETURNS (debou_left, debou_right, reset, 1Hz, 12Mhz);
INCLUDE "lpm_counter.inc";
SUBDESIGN guibrain
(left, right, clk, y_valid : IN
www.eeworm.com/read/5905/81019
tdf guibrain.tdf
FUNCTION debounce (left_button, right_button, clk)
RETURNS (debou_left, debou_right, reset, 1Hz, 12Mhz);
INCLUDE "lpm_counter.inc";
SUBDESIGN guibrain
(left, right, clk, y_valid : IN
www.eeworm.com/read/412366/11202661
bak divider.vhd.bak
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY divider IS
PORT(iCLK:in std_logic;--input,1KHz
oCLK:out std_logic);--output,1Hz
END divider;
ARCHITECTURE arch OF divider IS
SIGNAL cou