📄 clock.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY clock IS
PORT(clk: IN STD_LOGIC; --system clock,1hz
settime: IN STD_LOGIC; --recivedfrom "control" module
weekset: IN INTEGER RANGE 1 TO 8; --time from "control" module
hourhset: IN INTEGER RANGE 0 TO 2;
hourlset: IN INTEGER RANGE 0 TO 9;
minhset: IN INTEGER RANGE 0 TO 5;
minlset: IN INTEGER RANGE 0 TO 9;
sechset: IN INTEGER RANGE 0 TO 5;
seclset: IN INTEGER RANGE 0 TO 9;
weekdis: OUT INTEGER RANGE 1 TO 8; --time to be sent to "display" module
hourhdis: OUT INTEGER RANGE 0 TO 2; --time from "control" module
hourldis: OUT INTEGER RANGE 0 TO 9;
minhdis: OUT INTEGER RANGE 0 TO 5;
minldis: OUT INTEGER RANGE 0 TO 9;
sechdis: OUT INTEGER RANGE 0 TO 5;
secldis: OUT INTEGER RANGE 0 TO 9);
END clock;
ARCHITECTURE archi OF clock IS
SIGNAL seclow,minlow,hourlow: INTEGER RANGE 0 TO 9;
SIGNAL sechigh,minhigh: INTEGER RANGE 0 TO 5;
SIGNAL hourhigh: INTEGER RANGE 0 TO 2;
SIGNAL week: INTEGER RANGE 1 TO 8;
BEGIN
secldis<=seclow;
sechdis<=sechigh;
minldis<=minlow;
minhdis<=minhigh;
hourldis<=hourlow;
hourhdis<=hourhigh;
weekdis<=week;
normal_run: --this process finishes normal time running
PROCESS(clk,settime)
BEGIN
IF settime='1' THEN
seclow<=seclset;
sechigh<=sechset;
minlow<=minlset;
minhigh<=minhset;
hourlow<=hourlset;
hourhigh<=hourhset;
week<=weekset;
ELSE
IF clk='1' AND clk'event THEN
IF seclow=9 THEN
seclow<=0;
IF sechigh=5 THEN
sechigh<=0;
IF minlow=9 THEN
minlow<=0;
IF minhigh=5 THEN
minhigh<=0;
IF hourlow=9 THEN
hourlow<=0;
hourhigh<=hourhigh+1;
ELSIF hourlow=3 and hourhigh=2 THEN
hourhigh<=0;
hourlow<=0;
IF week=8 THEN
week<=1;
ELSIF week=6 THEN
week<=8;
ELSE week<=week+1;
END IF;
ELSE
hourlow<=hourlow+1;
END IF;
ELSE
minhigh<=minhigh+1;
END IF;
ELSE
minlow<=minlow+1;
END IF;
ELSE
sechigh<=sechigh+1;
END IF;
ELSE
seclow<=seclow+1;
END IF;
END IF;
END IF;
END PROCESS;
END archi;
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