代码搜索：水声信号
找到约 10,000 项符合「水声信号」的源代码
代码结果 10,000
www.eeworm.com/read/209602/15216772
vhd fen24.vhd
-------------------------------------------------
--实体名：fen24
--功 能：24进制计数器
--接 口：clk -时钟输入
-- qout1-个位BCD输出
-- qout2-十位BCD输出
-- carry-进位信号输出
-----------------------
www.eeworm.com/read/16789/690553
c i2c.c
#include
#include"ADS1115.h"
#include "I2C.h"
typedef unsigned char uchar;
typedef unsigned int uint;
unsigned int Initdata[4]={0};
/**************起始信号***************/
void star
www.eeworm.com/read/17631/746668
vhd scan_led.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity scan_led is
port(clk:in std_logic;--------------------------时钟信号
seg:out std_logic_vector(7 downto 0);-----
www.eeworm.com/read/17631/749085
vhd rom.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rom is
port(addr:in std_logic_vector(3 downto 0);------地址选择信号
en:in std_logic;---------------------------使能
www.eeworm.com/read/17885/763980
vhd fen24.vhd
-------------------------------------------------
--实体名：fen24
--功 能：24进制计数器
--接 口：clk -时钟输入
-- qout1-个位BCD输出
-- qout2-十位BCD输出
-- carry-进位信号输出
-----------------------
www.eeworm.com/read/32279/882216
vhd scan_led.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity scan_led is
port(clk:in std_logic;--------------------------时钟信号
seg:out std_logic_vector(7 downto 0);-----
www.eeworm.com/read/32279/884633
vhd rom.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rom is
port(addr:in std_logic_vector(3 downto 0);------地址选择信号
en:in std_logic;---------------------------使能
www.eeworm.com/read/39267/1125234
vhd scan_led.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity scan_led is
port(clk:in std_logic;--------------------------时钟信号
seg:out std_logic_vector(7 downto 0);-----
www.eeworm.com/read/39267/1127651
vhd rom.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rom is
port(addr:in std_logic_vector(3 downto 0);------地址选择信号
en:in std_logic;---------------------------使能
www.eeworm.com/read/492491/1173364
vhd counter.vhd
-- 库声明
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- 实体声明
entity counter is
generic (
MAX_COUNT : integer := 66 );
port (
clk : in std_logic;
reset_n : in std_logic; --复位信号
ce : i