fen24.vhd

CPLD VHDL CODE非常好的参考资料

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--实体名：fen24
--功  能：24进制计数器
--接  口：clk  -时钟输入
--        qout1-个位BCD输出
--        qout2-十位BCD输出
--        carry-进位信号输出

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity fen24 is 
port
(clk   : in  std_logic;
 rst   : in  std_logic;
 qout1 : out std_logic_vector(3 downto 0);
 qout2 : out std_logic_vector(3 downto 0);
 carry : out std_logic
);
end fen24;

architecture behave of fen24 is
signal tem1:std_logic_vector(3 downto 0);
signal tem2:std_logic_vector(3 downto 0);
begin
  process(clk,rst)
  begin
    if(rst='0')then
       tem1<="0010";
       tem2<="0001";
    elsif clk'event and clk='1' then 
       if (tem2="0010" and tem1="0011") then
           tem1<="0000";
           tem2<="0000";
           carry<='1';
       else
           carry<='0';
           if tem1="1001" then
              tem1<="0000";
              if tem2="1001" then
                 tem2<="0000";
              else
                 tem2<=tem2+1;
              end if;
           else
              tem1<=tem1+1;
           end if;
       end if;
    end if;
    qout1<=tem1;
    qout2<=tem2;
  end process;
end behave;