代码搜索：时钟提取
找到约 10,000 项符合「时钟提取」的源代码
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vhd key_led.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY key_led IS
PORT(
clk_48M: IN STD_LOGIC; --系统时钟(48MHz)
key: IN STD_LOGIC
www.eeworm.com/read/396392/8109906
c voice.c
#include "voice.h"
/* 延时t毫秒 */
void delay(uint t)
{
uint i;
while(t--)
{
/* 对于11.0592M时钟，约延时1ms */
for (i=0;i
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htm 79_1.htm
香巴拉 软件下载 - 应用软件 - 时钟日历 - [czy888.126.com]
td{font-size:9pt;line-height:140%}
body{fon
www.eeworm.com/read/295934/8132547
asm sx1302.asm
;天逸版实时时钟程序(未作测试，只供参考)
;***************************************************************************
;* ohm@szsxmcu.com 深圳随想电子科技有限公司版权所有 *
;* Create by :欧海明 www.szsxmcu.com 更多例程及单片机专业
www.eeworm.com/read/145600/12712763
txt e_clock.txt
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--时钟主程序
entity e_clock is
port(clk,key1,key2,fun_key3 :in std_logic;
a
www.eeworm.com/read/144235/12806174
#1 uart0.#1
#include
#include
//#include
/*修改时钟！！！！*/
/*帧错误和传输错误监测需要吗？查询方式？只是具有发送功能？*/
void UART0_transmit (unsigned int *samples, unsigned int numSample)
{
volatil
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#2 uart0.#2
#include
#include
//#include
/*修改时钟！！！！*/
/*帧错误和传输错误监测需要吗？查询方式？只是具有发送功能？*/
void UART0_transmit (unsigned int *samples, unsigned int numSample)
{
volatil
www.eeworm.com/read/144235/12806274
#3 uart0.#3
#include
#include
//#include
/*修改时钟！！！！*/
/*帧错误和传输错误监测需要吗？查询方式？只是具有发送功能？*/
void UART0_transmit (unsigned int *samples, unsigned int numSample)
{
volatil
www.eeworm.com/read/329792/12933516
vhd clock_6.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock_6 is
port(clk:in std_logic; --时钟输入20MHz
clr:in std_logic; --清零端
en:in std_logic; --暂停信号
m
www.eeworm.com/read/329792/12933717
bak clock_6.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock_6 is
port(clk:in std_logic; --时钟输入20MHz
clr:in std_logic; --清零端
en:in std_logic; --暂停信号
m