e_clock.txt

CHDL语言编写的数字时钟程序 具有时间显示

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--时钟主程序

entity e_clock is
   port(clk,key1,key2,fun_key3 :in   std_logic;
        alarm                  :out  std_logic :='0';
	     le_s2,le_s1            :out  std_logic_vector(3 downto 0) :="0000";
	     le_m2			      	 :out  std_logic_vector(3 downto 0) :="0000";
	     le_m1                  :out  std_logic_vector(3 downto 0) :="0000";
	     le_h2				       :out  std_logic_vector(3 downto 0) :="0000";
	     le_h1                  :out  std_logic_vector(3 downto 0) :="0000"
	     );  
end e_clock;

architecture Behavioral of e_clock is
signal fun_key,main_key1,main_key2		      :std_logic;
signal mode                                  :std_logic_vector(2 downto 0) :="000";
signal clkd                                  :std_logic; 
signal coun_dd1,coun_dm2,coun_dd2			   :std_logic_vector(3 downto 0);
signal coun_dm1                              :std_logic_vector(1 downto 0);
signal coun_cs1,coun_cs2,coun_cm2			   :std_logic_vector(3 downto 0);
signal coun_cm1,coun_ch2         			   :std_logic_vector(3 downto 0);
signal coun_ch1                              :std_logic_vector(1 downto 0);
signal coun_shs2,coun_shs1,coun_ss2,coun_ss1,coun_sm2,coun_sm1 :std_logic_vector(3 downto 0);
signal set_m2,set_m1,set_h2			        	:std_logic_vector(3 downto 0);
signal set_h1                                :std_logic_vector(1 downto 0);
signal Q1,Q2,Q3,Q4,Q5,Q6                     :std_logic;
    

component clock_run is
   port(clk             :in        std_logic;
        key1            :in        std_logic;
	     key2            :in        std_logic;
        mode            :in        std_logic_vector(2 downto 0) :="000";
	     clkd            :inout     std_logic;
	     coun_cs2	      :inout     std_logic_vector(3 downto 0) :="0000";
	     coun_cs1	      :inout     std_logic_vector(3 downto 0) :="0000";
	     coun_cm2	      :inout     std_logic_vector(3 downto 0) :="0000";
	     coun_cm1	      :inout     std_logic_vector(3 downto 0) :="0000";
        coun_ch2	      :inout     std_logic_vector(3 downto 0) :="0000";
        coun_ch1        :inout     std_logic_vector(1 downto 0) :="00"
	     );
end component;

component sclk_run is
   port(clk             :in     std_logic;
        key1            :in     std_logic;
        key2            :in     std_logic;
	     mode            :in     std_logic_vector(2 downto 0);
        coun_shs1,coun_shs2   :inout std_logic_vector(3 downto 0);
        coun_ss1,coun_ss2     :inout std_logic_vector(3 downto 0);
	     coun_sm1,coun_sm2     :inout std_logic_vector(3 downto 0)
        );
end component;

component alarm_set is
   port(clk,key1,key2	    :in    std_logic;
	     mode                :in    std_logic_vector(2 downto 0);
	     set_m2,set_m1	    :inout	std_logic_vector(3 downto 0);
	     set_h2              :inout std_logic_vector(3 downto 0);
	     set_h1              :inout std_logic_vector(1 downto 0)
	     );
end component;

component date is
   port(clk,key1,key2     :in     std_logic;
        mode              :in     std_logic_vector(2 downto 0);
	     clkd              :in     std_logic;
	     coun_dm2,coun_dd1 :inout  std_logic_vector(3 downto 0);
	     coun_dm1		     :inout  std_logic_vector(1 downto 0);
	     coun_dd2          :inout  std_logic_vector(3 downto 0)
	     );
end component;

begin
u1:clock_run port map(clk=>clk,key1=>key1,key2=>key2,mode=>mode,
                      clkd=>clkd,coun_cs2=>coun_cs2,coun_cs1=>coun_cs1,
							 coun_cm2=>coun_cm2,coun_cm1=>coun_cm1,coun_ch2=>coun_ch2,
							 coun_ch1=>coun_ch1
				          );

u2:sclk_run  port map(clk=>clk,key1=>key1,key2=>key2,mode=>mode,coun_shs1=>coun_shs1,
                      coun_shs2=>coun_shs2,coun_ss1=>coun_ss1,coun_ss2=>coun_ss2,
				          coun_sm1=>coun_sm1,coun_sm2=>coun_sm2);

u3:alarm_set port map(clk=>clk,key1=>key1,key2=>key2,mode=>mode,set_m2=>set_m2,
				          set_m1=>set_m1,set_h2=>set_h2,set_h1=>set_h1);

u4:date      port map(clk=>clk,key1=>key1,key2=>key2,mode=>mode,clkd=>clkd,
                      coun_dm1=>coun_dm1,coun_dd1=>coun_dd1,coun_dm2=>coun_dm2,
				          coun_dd2=>coun_dd2);

sny_pro:process(clk,key1,key2,fun_key3,Q1,Q2,Q3,Q4,Q5,Q6)
begin
   if(clk='1'and clk'event)then		 --输入信号同步--
	   Q1<=fun_key3;
		Q2<=Q1;
		Q3<=key1;
		Q4<=Q3;
		Q5<=key2;
		Q6<=Q5;				
	end if;
	fun_key<=Q1 and not Q2;
	main_key1<=Q3 and not Q4;
	main_key2<=Q5 and not Q6;
end process;

mode_pro:process(clk,fun_key,mode)
begin
   if(clk='1'and clk'event)then
	   if(fun_key='1')then
		   if(mode>="100")then
		      mode<="000";
		   else
		      mode<=mode+'1';
		   end if;
	   end if;
	end if;
end process;

dispaly_pro:process(mode,clk,main_key1,main_key2)
begin
   if(clk='1' and clk'event)then
	   case mode is
	      when "000" =>
		      if(main_key1='1')then
				    le_s2<="0000";
				    le_s1<="0000";
				    le_m2<=set_m2;
				    le_m1<=set_m1;
				    le_h2<=set_h2;
				    le_h1(1 downto 0)<=set_h1;
				    le_h1(3 downto 2)<="00";
		      elsif(main_key2='1')then
				    le_s2<="0000";
				    le_s1<="0000";
				    le_m2<=coun_dd2;
				    le_m1<=coun_dd1;
				    le_h2<=coun_dm2;
				    le_h1(1 downto 0)<=coun_dm1;
				    le_h1(3 downto 2)<="00";
		      else
				    le_s2<=coun_cs2;
				    le_s1<=coun_cs1;
				    le_m2<=coun_cm2;
				    le_m1<=coun_cm1;
				    le_h2<=coun_ch2;
				    le_h1(1 downto 0)<=coun_ch1;
				    le_h1(3 downto 2)<="00";
		      end if;
		   when "001" =>
				    le_s2<=coun_cs2;
				    le_s1<=coun_cs1;
				    le_m2<=coun_cm2;
				    le_m1<=coun_cm1;
				    le_h2<=coun_ch2;
				    le_h1(1 downto 0)<=coun_ch1;
				    le_h1(3 downto 2)<="00";
		   when "010" =>
				    le_s2<=coun_shs2;
				    le_s1<=coun_shs1;
				    le_m2<=coun_ss2;
				    le_m1<=coun_ss1;
				    le_h2<=coun_sm2;
				    le_h1<=coun_sm1;
		   when "011" =>
				    le_s2<="0000";
				    le_s1<="0000";
				    le_m2<=set_m2;
				    le_m1<=set_m1;
				    le_h2<=set_h2;
				    le_h1(1 downto 0)<=set_h1;
				    le_h1(3 downto 2)<="00"; 
		   when "100" =>
				    le_s2<="0000";
				    le_s1<="0000";
				    le_m2<=coun_dd2;
				    le_m1<=coun_dd1;
				    le_h2<=coun_dm2;
				    le_h1(1 downto 0)<=coun_dm1;
				    le_h1(3 downto 2)<="00";
		   when others      =>
		    		 null;
	   end case;
   end if;
end process;

alarm_pro:process(clk,set_m2,coun_cm2,set_m1,coun_cm1,set_h2,coun_ch2,set_h1,coun_ch1)
begin
   if(clk='1' and clk'event)then
      if(set_m2=coun_cm2 and set_m1=coun_cm1 and set_h2=coun_ch2 and set_h1=coun_ch1)then
         alarm<='1';
	   else
	      alarm<='0';
	   end if;
   else
   end if;
end process;   	         	    
end Behavioral;

 --*********************************************************************--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clock_run is
   port(clk             :in        std_logic;
        key1            :in        std_logic;
	     key2            :in        std_logic;
        mode            :in        std_logic_vector(2 downto 0) :="000";
	     clkd            :out       std_logic;
	     coun_cs2	      :inout     std_logic_vector(3 downto 0) :="0000";
	     coun_cs1	      :inout     std_logic_vector(3 downto 0) :="0000";
	     coun_cm2	      :inout     std_logic_vector(3 downto 0) :="0000";
	     coun_cm1	      :inout     std_logic_vector(3 downto 0) :="0000";
        coun_ch2	      :inout     std_logic_vector(3 downto 0) :="0000";
        coun_ch1        :inout     std_logic_vector(1 downto 0) :="00"
	   );
end clock_run;

architecture Behavioral of clock_run is
signal counter64     :std_logic_vector(4 downto 0) :="00000";
signal counter16     :std_logic_vector(3 downto 0) :="0000";
signal clk64,clk1hz  :std_logic ;
signal clkm,clkh     :std_logic ;
signal key1c,key2c,enclkm,enclkh :std_logic;
signal Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8   :std_logic;
begin
   keyc_pro:process(clk,mode,key1,key2,clkm,clkh)
	begin
	if(clk='1'and clk'event)then
	   if(mode="001")then		 --输入信号同步--
			Q1<=key1;
			Q2<=Q1;
			Q3<=key2;
			Q4<=Q3;
		else
			Q5<=clkm;
			Q6<=Q5;
			Q7<=clkh;
			Q8<=Q7;				
		end if;
		key1c<=Q1 and not Q2;
		key2c<=Q3 and not Q4;
		enclkm<=Q5 and not Q6;
		enclkh<=Q7 and not Q8;
	end if;
	end process;

   clock_div:process(mode,clk,clk64)
   begin
   if(clk='1' and clk'event)then
      if(mode/="001")then
         if(counter64>="11111")then
	         counter64<="00000";
	         clk64<='1';
	      else
	         counter64<=counter64+'1';
		      clk64<='0';
	      end if;
	   end if;
		if(clk64='1')then
		   if(counter16>="1111")then
			   counter16<="0000";
			   clk1hz<='1';
			else
			   counter16<=counter16+'1';
			end if;
		else
			clk1hz<='0';		   
	   end if;
	end if;
   end process;

   clock_pro:process(clk,enclkm,enclkh,mode,key1c,key2c,clk1hz)
   begin
	if(clk='1'and clk'event)then
	   if(mode/="001")then
	      if(clk1hz='1')then
		      if(coun_cs2="1001" and coun_cs1="0101")then
				   coun_cs2<="0000";
				   coun_cs1<="0000";
				   clkm<='1';
				elsif(coun_cs2="1001")then
				   coun_cs2<="0000";
				   coun_cs1<=coun_cs1+'1';
				   clkm<='0';
				else
				   coun_cs1<=coun_cs1;
				   coun_cs2<=coun_cs2+'1';
				   clkm<='0';
				end if;
		   end if;		
		   if(enclkm='1')then
		      if(coun_cm2="1001" and coun_cm1="0101")then
				   coun_cm2<="0000";
				   coun_cm1<="0000";
				   clkh<='1';
				elsif(coun_cm2="1001")then
				   coun_cm2<="0000";
				   coun_cm1<=coun_cm1+'1';
				   clkh<='0';
				else
				   coun_cm1<=coun_cm1;
				   coun_cm2<=coun_cm2+'1';
				   clkh<='0';
				end if;
			end if;					 
		   if(enclkh='1')then
		      if(coun_ch2="0011" and coun_ch1="10")then
				   coun_ch2<="0000";
				   coun_ch1<="00";
				   clkd<='1';
				elsif(coun_ch2="1001")then
				   coun_ch2<="0000";
				   coun_ch1<=coun_ch1+'1';
				   clkd<='0';
				else
				   coun_ch1<=coun_ch1;
				   coun_ch2<=coun_ch2+'1';
				   clkd<='0';
		      end if;
			end if;
	   else
			if(key2c='1')then
				if(coun_ch2="0011" and coun_ch1="10")then
					coun_ch2<="0000";
					coun_ch1<="00";
			   elsif(coun_ch2="1001")then
					coun_ch2<="0000";
					coun_ch1<=coun_ch1+'1';
				else
					coun_ch1<=coun_ch1;
					coun_ch2<=coun_ch2+'1';
			   end if;
		   elsif(key1c='1')then
				if(coun_cm2="1001" and coun_cm1="0101")then
					coun_cm2<="0000";
					coun_cm1<="0000";
				elsif(coun_cm2="1001")then
					coun_cm2<="0000";
					coun_cm1<=coun_cm1+'1';
			   else
					coun_cm1<=coun_cm1;
					coun_cm2<=coun_cm2+'1';
			   end if;
			end if;	 							  	       	   
	   end if;
	end if;
   end process;	  
end Behavioral;