代码搜索：序列信号
找到约 10,000 项符合「序列信号」的源代码
代码结果 10,000
www.eeworm.com/read/216262/15022617
m example6_15.m
%装载原始信号并图示之
load noismima;
s=noismima(1:1000);
subplot(2,2,1);
plot(s);
title('原始信号');
%==============================
%采用默认阈值、用wdencmp函数进行消噪处理
[thr,sorh,keepapp,crit]=ddencmp('den','wp',s);
www.eeworm.com/read/215911/15034228
m example6_17.m
%装载源信号
load noisbump;
s=noisbump(1:1000);
subplot(2,1,1);
plot(s);
title('原始信号');
%==============================
%采用默认阈值，以小波包函数wpdencmp对s进行压缩处理
[thr,sorh,keepapp,crit]=ddencmp('cmp','wp',s);
www.eeworm.com/read/215911/15034237
m example6_15.m
%装载原始信号并图示之
load noismima;
s=noismima(1:1000);
subplot(2,2,1);
plot(s);
title('原始信号');
%==============================
%采用默认阈值、用wdencmp函数进行消噪处理
[thr,sorh,keepapp,crit]=ddencmp('den','wp',s);
www.eeworm.com/read/215382/15062857
m conv_example.m
%conv_example.m
%计算卷积的例子
u = ones(1,15); %阶跃信号
v = zeros(1,25);
v(5:25) = 0:1/20:1; %线性信号
w=conv(u,v); %卷积
subplot(3,1,1); %画
www.eeworm.com/read/215382/15062862
m fliter_example.m
%filter_example.m
%对带噪声的正弦信号进行平均值滤波
t=0:0.1:10; %时间
n = 6*randn(size(t)); %高斯白噪声
x = 40*sin(t)+n; %在正弦信号中添加噪声
a = 1;
www.eeworm.com/read/17522/734315
vhd valid_signal.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--防抖动程序，确保输入的信号为有效信号；
entity valid_signal is
Port (clk : in std
www.eeworm.com/read/17631/743997
vhd fenpinpwm20m_10k.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpinpwm20M_10k is
port(
clk:in std_logic; ------时钟信号20MhZ
fout:out std_logic); -----频率信号输
www.eeworm.com/read/17631/744000
vhd fenpinadc0809.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpinadc0809 is
port(
clk:in std_logic; ------时钟信号20MhZ
fout:out std_logic); -----频率信号输出500K
www.eeworm.com/read/17631/745510
vhd clock.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock is
port(clk:in std_logic;-----时钟输入 20mhz
clr:in std_logic;-----清零信号
en:in std_logic;------暂停信号
www.eeworm.com/read/17631/746464
vhd led.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity led is
port(clk:in std_logic;-----时钟信号
rst:in std_logic;-----系统复位信号
q: out std_logic_vector(7 downto