valid_signal.vhd

一些很好的FPGA设计实例

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--防抖动程序，确保输入的信号为有效信号；
entity valid_signal is		                
    Port (clk  : in std_logic;
	     din  : in std_logic;
		dout : out std_logic );
end valid_signal;

architecture Behavioral of valid_signal is

begin
process(clk,din)
variable cnt : std_logic_vector(1 downto 0);
begin
   if din='1' then cnt:="00";
	elsif clk'event and clk='1' then
	   if cnt<"10" then cnt:=cnt+1;
	   end if;
   end if;

	dout<=cnt(1);

end process;

end Behavioral;