代码搜索：序列信号
找到约 10,000 项符合「序列信号」的源代码
代码结果 10,000
www.eeworm.com/read/464287/7166692
m a44.m
%装载源信号
load noisbump;
s=noisbump(1:1000);
subplot(2,1,1);
plot(s);
title('原始信号');
%==============================
%采用默认阈值，以小波包函数wpdencmp对s进行压缩处理
[thr,sorh,keepapp,crit]=ddencmp('cmp','wp',s);
www.eeworm.com/read/461349/7228688
m bpsk_pet.m
echo off
m=10000;
ran(1,1:m)=randn(1,m);
a=zeros(1,m); %随机产生qpsk的信号比特1或-1=zeros(1,m);
%随机产生2psk的信号比特1或-1
for i=1:m
www.eeworm.com/read/461349/7228693
m bpsk_pe.m
echo off
m=10000;
ran(1,1:m)=randn(1,m);
a=zeros(1,m); %随机产生qpsk的信号比特1或-1=zeros(1,m);
%随机产生2psk的信号比特1或-1
for i=1:m
www.eeworm.com/read/461162/7232489
m dm10202.m
% dm10202
% 冲激信号的傅里叶变换及频谱分析
syms t w ; %定义符号变量
ut1 = sym('Heaviside(t+0.5)-Heaviside(t-0.5)'); %脉宽为1的矩形脉冲信号
subplot(211);
www.eeworm.com/read/459044/7283922
m framestatusconversiondemoresult3.m
>> whos
Name Size Bytes Class
FrameFmt 6x2 96 double array % 基于帧的信号
SampleOut 2x2x3 96 double array % 基于样值的信号
SmplFmt 2x2x3 96 doub
www.eeworm.com/read/398993/7904150
vhd ask.vhd
library ieee;
use ieee.std_logic_1164.all;
entity ask is
port(clk: in std_logic;--系统时钟
start: in std_logic;--启动信号
base_input: in std_logic;--基带信号
ask: out std_logic;--已调
www.eeworm.com/read/329796/12932341
vhd 复件 led.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity led is
port(clk:in std_logic; --时钟信号
rst:in std_logic; --系统复位信号
q:out std_logic_vector(7 downto 0))
www.eeworm.com/read/329796/12932672
bak led.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity led is
port(clk:in std_logic; --时钟信号
rst:in std_logic; --系统复位信号
q:out std_logic_vector(7 downto 0))
www.eeworm.com/read/329796/12932675
vhd led.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity led is
port(clk:in std_logic; --时钟信号
rst:in std_logic; --系统复位信号
q:out std_logic_vector(7 downto 0))
www.eeworm.com/read/321347/13408431
vhd addr.vhd
LIBRARY IEEE; --正弦信号发生器源文件
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ADDR IS
PORT ( CLK : IN STD_LOGIC; --信号源时钟
Q : OUT STD_LOGIC_VEC