ask.vhd

提供一个把通信中ASK调制用VHDL来实现的例子

library ieee;
use ieee.std_logic_1164.all;

entity ask is
  port(clk: in std_logic;--系统时钟
       start: in std_logic;--启动信号
       base_input: in std_logic;--基带信号
       ask: out std_logic;--已调波
       base_output: out std_logic);--解调输出
end ask;

architecture behav of ask is
component ask_encoder --引入调制器件
  port(clk: in std_logic; 
       base_input: in std_logic; 
       start: in std_logic; 
       ask_output: out std_logic); 
end component;
component ask_decoder --引入解调器件
  port(clk: in std_logic; 
       start: in std_logic; 
       ask_input: in std_logic; 
       base_output: out std_logic);
end component;
  signal ask1: std_logic; --中间信号(已调波)
begin
  u1:ask_encoder port map(clk,base_input,start,ask1); --例化调制器件并进行端口映射
  u2:ask_decoder port map(clk,start,ask1,base_output); --例化解调器件并进行端口映射
  ask <= ask1;
end behav;