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doc 06 Σ Δ模数转换器 .doc
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pdf 出租车计价器.pdf
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pdf 电子变压器设计手册.pdf
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pdf 反激变压器计算.pdf
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pdf 系统管理器.pdf
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exe 51乐普编辑器.exe
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pdf 仿真器原理图.pdf
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jpg 430jtag仿真器.jpg
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txt 序列检测器verilog代码.txt
module seqdet(x,z,clk,rst,state);
input x,clk,rst;
output z;
output [2:0] state;
reg [2:0] state;
wire z;
parameter IDLE='d0,A='d1,B='d2,C='d3,D='d4,E='d5;
assign z=(state==E && x==0)?1:0;
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