序列检测器verilog代码.txt

序列检测器

module seqdet(x,z,clk,rst,state);
input x,clk,rst;
output z;
output [2:0] state;
reg [2:0] state;
wire z;

parameter IDLE='d0,A='d1,B='d2,C='d3,D='d4,E='d5;

 assign z=(state==E && x==0)?1:0;

always @(posedge clk)
      if(!rst)
        begin
          state<=IDLE;
         end
      else
          casex(state)
              IDLE:if(x==1)
                    begin
                       state<=A;
                    end
                   else
                      begin
                        state<=IDLE;
                      end
                  A: if(x==0)
                        begin
                          state<=B;
                        end
                     else
                        begin
                          state<=A;
                        end

                  B:if(x==0)
                      begin
                         state<=C;
                       end
                     else
                        begin
                          state<=A;
                        end
                   C:if(x==1)
                        begin
                           state<=D;
                        end
                      else
                        begin
                           state<=IDLE;
                        end
                    D:if(x==0)
                        begin
                          state<=E;
                        end
                       else
                          begin
                             state<=A;
                          end
                     E: if(x==0)
                         begin
                            state<=C;
                         end
                        else
                           begin
                              state<=A;
                           end
               default:state<=IDLE;
                endcase
endmodule