代码搜索:定点DSP

找到约 10,000 项符合「定点DSP」的源代码

代码结果 10,000
www.eeworm.com/read/110819/15524468

dsp a.dsp

# Microsoft Developer Studio Project File - Name="a" - Package Owner= # Microsoft Developer Studio Generated Build File, Format Version 6.00 # ** DO NOT EDIT ** # TARGTYPE "Win32 (x86) Console
www.eeworm.com/read/104986/15680212

dsp 调试.dsp

# Microsoft Developer Studio Project File - Name="调试" - Package Owner= # Microsoft Developer Studio Generated Build File, Format Version 6.00 # ** DO NOT EDIT ** # TARGTYPE "Win32 (x86) Applic
www.eeworm.com/read/103548/15729453

dsp 期权.dsp

# Microsoft Developer Studio Project File - Name="期权" - Package Owner= # Microsoft Developer Studio Generated Build File, Format Version 6.00 # ** DO NOT EDIT ** # TARGTYPE "Win32 (x86) Applic
www.eeworm.com/read/102901/15752760

dsp a.dsp

# Microsoft Developer Studio Project File - Name="a" - Package Owner= # Microsoft Developer Studio Generated Build File, Format Version 6.00 # ** DO NOT EDIT ** # TARGTYPE "Win32 (x86) Console
www.eeworm.com/read/102677/15763083

dsp 银行.dsp

# Microsoft Developer Studio Project File - Name="银行" - Package Owner= # Microsoft Developer Studio Generated Build File, Format Version 6.00 # ** DO NOT EDIT ** # TARGTYPE "Win32 (x86) Consol
www.eeworm.com/read/149576/12364677

txt 16×16位定点数加、减法子程序.txt

;【校验举例2】 26222+3000=29222(十进制) ;化为十六进制数: 666EH+0BB8H ;结果:7226H(十六进制) ;【例程】 ;2 四则运算子程序 ; 2.1 16×16位定点数加、减法子程序 ;以下子程序实现2个16×16位有符号数加、减运算,其和或差用一个16位数表示。 ;在子程序中,减法是通过对减数求补后再与被减数相加来实现的。因此,当程序 ; ...
www.eeworm.com/read/149576/12364699

txt 8×8位定点数乘法子程序(速度).txt

;******************************************************************* ; 8x8 Software Multiplier ; ( Fast Version : Straight Line Code ) ;*****************************
www.eeworm.com/read/149576/12364713

txt 8×8位定点数乘法子程序(容量).txt

;******************************************************************* ; 8x8 Software Multiplier ; ( Code Efficient : Looped Code ) ;**********************************
www.eeworm.com/read/287040/8729304

v mesure_top_tb.v

`timescale 1ns/1ns module mesure_top_tb; reg clk,rst; wire [7:0] qd; wire H_sig,V_sig,qfv,qck; wire [15:0] s_fifo_rdb; wire [10:0] sa,sa_dsp; wire [1:0] ba,ba_dsp; wire [31:0] dq; wire [15:0]
www.eeworm.com/read/384663/8852258

v mesure_top_tb.v

`timescale 1ns/1ns module mesure_top_tb; reg clk,rst; wire [7:0] qd; wire H_sig,V_sig,qfv,qck; wire [15:0] s_fifo_rdb; wire [10:0] sa,sa_dsp; wire [1:0] ba,ba_dsp; wire [31:0] dq; wire [15:0]