mesure_top_tb.v

来自「视频采集」· Verilog 代码 · 共 96 行

`timescale 1ns/1ns
module mesure_top_tb;
reg	clk,rst;
wire	[7:0]	qd;
wire	H_sig,V_sig,qfv,qck;
wire	[15:0]	s_fifo_rdb;
wire	[10:0]	sa,sa_dsp;
wire	[1:0]	ba,ba_dsp;
wire	[31:0]	dq;
wire	[15:0]	dq_dsp;
wire	[3:0]	dqm;
reg	clk40m;
reg	clk25m;
reg	clk27m;

initial
   begin
      clk = 0;
      clk40m = 0;
      clk27m = 0;
      rst = 0;
      #100 rst =1;
      clk25m = 0;
   end
   
always #10 clk = !clk;
always #12.5 clk40m = ~clk40m;
always #20 clk25m = !clk25m;
always #18.5 clk27m = !clk27m;

mesure_card_top mesure_top(
	.clkin  (clk),
	.rst  (rst),
	.H_sig(H_sig),
	.V_sig(V_sig),
	.odd_even_sig(odd_even_out),
	.qd   (qd),
	.qck  (clk27m),
       
	.dq    (dq)   , 
	.sa  (sa) , 
	.ba    (ba)   ,  
	.cke   (cke)  , 
	.cs_n  (cs_n) , 
	.ras_n (ras_n), 
	.cas_n (cas_n), 
	.we_n  (we_n) ,
	.sdram_clk(sdram_clk),
	.dqm(dqm),
	.mode_vga(1'b1),
	
	.dq_dsp    (dq_dsp)   , 
	.sa_dsp    (sa_dsp) , 
	.ba_dsp    (ba_dsp)   ,  
	.cke_dsp   (cke_dsp)  , 
	.cs_n_dsp  (cs_n_dsp) , 
	.ras_n_dsp (ras_n_dsp), 
	.cas_n_dsp (cas_n_dsp), 
	.we_n_dsp  (we_n_dsp),
	.clk40m(clk40m) 
                 
);
mt48lc2m32b2 sdram1(
         .Dq    (dq)   , 
         .Addr  (sa) , 
         .Ba    (ba)   , 
         .Clk   (clk)  , 
         .Cke   (cke)  , 
         .Cs_n  (cs_n) , 
         .Ras_n (ras_n), 
         .Cas_n (cas_n), 
         .We_n  (we_n) , 
         .Dqm   (4'b0)
         );
mt48lc2m16b2 sdram2(
         .Dq    (dq_dsp)   , 
         .Addr  (sa_dsp) , 
         .Ba    (ba_dsp)   , 
         .Clk   (clk_dsp)  , 
         .Cke   (cke_dsp)  , 
         .Cs_n  (cs_n_dsp) , 
         .Ras_n (ras_n_dsp), 
         .Cas_n (cas_n_dsp), 
         .We_n  (we_n_dsp) , 
         .Dqm   (4'b0)
         );
             
image_NTSC image1(	
	.rst(rst),
	.clk27m(clk27m),
	.qd(qd),
	.hsync(H_sig),
	.vsync(V_sig),
	.odd_even_out(odd_even_out)
	);	           
 endmodule