代码搜索：信号失真
找到约 10,000 项符合「信号失真」的源代码
代码结果 10,000
www.eeworm.com/read/32279/882216
vhd scan_led.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity scan_led is
port(clk:in std_logic;--------------------------时钟信号
seg:out std_logic_vector(7 downto 0);-----
www.eeworm.com/read/32279/884633
vhd rom.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rom is
port(addr:in std_logic_vector(3 downto 0);------地址选择信号
en:in std_logic;---------------------------使能
www.eeworm.com/read/39267/1125234
vhd scan_led.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity scan_led is
port(clk:in std_logic;--------------------------时钟信号
seg:out std_logic_vector(7 downto 0);-----
www.eeworm.com/read/39267/1127651
vhd rom.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rom is
port(addr:in std_logic_vector(3 downto 0);------地址选择信号
en:in std_logic;---------------------------使能
www.eeworm.com/read/492491/1173364
vhd counter.vhd
-- 库声明
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- 实体声明
entity counter is
generic (
MAX_COUNT : integer := 66 );
port (
clk : in std_logic;
reset_n : in std_logic; --复位信号
ce : i
www.eeworm.com/read/489429/1224516
asm diir.asm
.title "diir1.asm"
.mmregs
.global start
.def start,_c_int00
N .set 6
.copy "IIRIN.inc" ;输入信号x(n)数据
table ;IIR滤波器系数
.word 63
.word 0
www.eeworm.com/read/453029/1646567
vhd fen24.vhd
-------------------------------------------------
--实体名：fen24
--功 能：24进制计数器
--接 口：clk -时钟输入
-- qout1-个位BCD输出
-- qout2-十位BCD输出
-- carry-进位信号输出
-----------------------
www.eeworm.com/read/235687/4646147
asm speed_pr.asm
;===========================================================================
; 文件名: Speed_pr.asm
;
; 模块名: SPEED_PRD
;
; 初始化程序: SPEED_PRD_INIT
;
; 公司: 达盛科技
;
; 功能描述: 同过测量传感器输出的信号周期来
www.eeworm.com/read/328695/3438229
vhd scan_led.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity scan_led is
port(clk:in std_logic;--------------------------时钟信号
seg:out std_logic_vector(7 downto 0);-----
www.eeworm.com/read/328695/3439568
vhd rom.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rom is
port(addr:in std_logic_vector(3 downto 0);------地址选择信号
en:in std_logic;---------------------------使能