rom.vhd

来自「大量VHDL写的数字系统设计有用实例达到」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rom is
port(addr:in std_logic_vector(3 downto 0);------地址选择信号
     en:in std_logic;---------------------------使能端
     data:out std_logic_vector(7 downto 0));----数据输出端
end;
architecture one of rom is
	type memory is array(0 to 15)of std_logic_vector(7 downto 0);---定义数据类型
	signal data1:memory:=("10101001","11111101","11101001","11011100",--数据
					     "10111001","11000010","11000101","00000100",
						 "11101100","10001010","11001111","00110100",
						 "11000001","10011111","10100101","01011100");
	signal addr1:integer range 0 to 15;
begin
	addr1<=conv_integer(addr);-----二进制到十进制的转换
process(en,addr1,addr,data1)
begin
if en='1' then 
   data<=data1(addr1);
else 
   data<=(others=>'Z');
end if;
end process;
end;