代码搜索：低功耗CMOS

找到约 2,363 项符合「低功耗CMOS」的源代码

代码结果 2,363
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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sp p8-24.sp

*EXERCISE8_11_2CMOS INVERTER FOR CHANGING W .options post=2 list M1 2 1 3 3 MP L=2u W=10.80600u M2 2 1 0 0 MN L=2u W=4u VDD 3 0 DC 5V VIN 1 0 DC 2.5V .MODEL MP PMOS (level
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sp tran.sp

* Bandgap Voltage Reference start up simulation * Set options .option post probe .include cmos06.mod .param Ls=1.6u L0=3u W1=30u W2=20u r2=45k m1 13 1 vdd vdd cmosp w=W1 l=L0 as='Ls
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c hd.c

/* passed * linux/kernel/hd.c * * (C) 1991 Linus Torvalds */ #include /* * 本程序是底层硬盘中断辅助程序。主要用于扫描请求列表，使用中断在函数之间跳转。 * 由于所有的函数都是在中断里调用的，所以这些函数不可以睡眠。请特别注意。 * 由Drew Eckhardt 修改，利用CMOS 信息检测硬盘数
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sp fig33_45.sp

* Figure 33.45 CMOS: Mixed-Signal Circuit Design * Vdd Vdd 0 DC 1.5 Vin Vin 0 DC 0 pulse 0 1.5 2n .1n .1n 5.9n 17n Vclk clk 0 DC 0 pulse 0 1.5 0 .1n .1n 4.9n 10n X1 Vin Vout clk vdd dtspc
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sp fig33_44.sp

* Figure 33.44 CMOS: Mixed-Signal Circuit Design * Vdd Vdd 0 DC 1.5 Vin Vin 0 DC 0 pulse 0 1.5 2n .1n .1n 5.9n 17n Vphi phi 0 DC 0 pulse 0 1.5 0 .2n .2n 4.8n 10n Vphib phib 0 DC 0 pulse 0 1.5 5
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sp fig33_30.sp

* Figure 33.30 CMOS: Mixed-Signal Circuit Design * M1 Vd1 Vg Vs Vb nmos W=10 L=1 M2 Vd2 Vg Vs Vb nmos W=20 L=1 M3 Vd3 Vg Vs Vb nmos W=50 L=1 Vg Vg 0 DC 2.3 Vs Vs 0 DC 1.5 Vd Vd 0 DC 1.5
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sp fig33_43.sp

* Figure 33.43 CMOS: Mixed-Signal Circuit Design * Vdd Vdd 0 DC 1.5 Vin Vin 0 DC 0 pulse 0 1.5 2n .1n .1n 5.9n 17n Vphi phi 0 DC 0 pulse 0 1.5 0 .2n .2n 4.8n 10n Vphib phib 0 DC 0 pulse 0 1.5 5
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sp fig33_29.sp

* Figure 33.29 CMOS: Mixed-Signal Circuit Design * M1 Vd1 Vg Vs Vb nmos W=10 L=1 M2 Vd2 Vg Vs Vb nmos W=20 L=1 M3 Vd3 Vg Vs Vb nmos W=50 L=1 Vg Vg 0 DC 1.5 Vs Vs 0 DC 1.5 Vd Vd 0 DC 1.5
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sp fig33_33.sp

* Figure 33.33 CMOS: Mixed-Signal Circuit Design * Vdd Vdd 0 DC 1.5 Vin Vin 0 DC 0 pulse 0 1.5 0 .1n .1n 4.9n 10n X1 Vin phi2d norout1 Vdd nor X2 Vin Vinb Vdd invert X3 Vinb phi1d norout2 Vd
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www.eeworm.com/read/376085/9332711

sp fig33_23.sp

* Figure 33.23 CMOS: Mixed-Signal Circuit Design * M1 Vd1 Vg Vs Vb nmos W=10 L=1 M2 Vd2 Vg Vs Vb nmos W=20 L=1 M3 Vd3 Vg Vs Vb nmos W=50 L=1 Vg Vg 0 DC 1.5 Vs Vs 0 DC 0 Vd Vd 0 DC 1.5 V
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